Figure 7-2 Gpio Circuit Diagram - Motorola DSP56012 User Manual

• When the GCx bit is cleared and the GDDx bit is cleared (the pin is defined as
an input), the corresponding GPIOx pin input buffer is disconnected from the
pin and does not require an external pull-up (see Table 7-1 and Figure 7-2).
• When the GCx bit is set and the GDDx bit is cleared (the pin is defined as
input), the corresponding GPIOx pin input buffer is connected to the pin (see
Table 7-1 and Figure 7-2).
• When the GCx bit is cleared and the GDDx bit is set (the pin is defined as
output), the corresponding GPIOx pin output buffer is defined as a standard
active high/active low type (see Table 7-1 and Figure 7-2).
• When the GCx bit is set and the GDDx bit is set (the pin is defined as output),
the corresponding GPIOx pin output buffer is defined as an open-drain type
(see Table 7-1 and Figure 7-2).
The GC[7:0] bits are cleared during hardware reset and software reset.
GD0–GD7
MOTOROLA
GDD
*
See Table 7-1 GPIO Pin Configuration.

Figure 7-2 GPIO Circuit Diagram

DSP56012 User's Manual
GPIO Register (GPIOR)
GDD
GC
GDD
Buffer
Control*
GPIO
PIN
AA0442k
7-5