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Serial Host Interface
SHI Programming Considerations
• SCK/SCL is the SCL serial clock output.
• MISO/SDA is the SDA open drain serial data line.
• MOSI/HA0 is the HA0 slave device address input.
• SS/HA2 is the HA2 slave device address input.
• HREQ is the Host Request input.
2
In the I
C Master mode, a data transfer session is always initiated by the DSP by
writing to the HTX register when HIDLE is set. This condition ensures that the data
byte written to HTX will be interpreted as being a slave address byte. This data byte
must specify the slave device address to be selected and the requested data transfer
direction.
Note: The slave address byte should be located in the high portion of the data word,
whereas the middle and low portions are ignored. Only one byte (the slave
address byte) will be shifted out, independent of the word length defined by
the HM0–HM1 bits.
In order for the DSP to initiate a data transfer the following actions are to be
performed:
• The DSP tests the HIDLE status bit.
• If the HIDLE status bit is set, the DSP writes the slave device address and the
R/W bit to the most significant byte of HTX.
• The SHI generates a start event.
• The SHI transmits one byte only, internally samples the R/W direction bit
(last bit), and accordingly initiates a receive or transmit session.
• The SHI inspects the SDA level at the ninth clock pulse to determine the ACK
value. If acknowledged (ACK = 0), it starts its receive or transmit session
according to the sampled R/W value. If not acknowledged (ACK = 1), the
HBER status bit in HCSR is set, which will cause an SHI Bus Error interrupt
request if HBIE is set, and a stop event will be generated.
The HREQ input pin is ignored by the I
cleared, and considered if either of them is set. When asserted, HREQ indicates that
the external slave device is ready for the next data transfer. As a result, the I
device sends clock pulses for the full data word transfer. HREQ is deasserted by the
external slave device at the first clock pulse of the next data transfer. When
deasserted, HREQ will prevent the clock generation of the next data word transfer
until it is asserted again. Connecting the HREQ line between two SHI-equipped
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2
C master device if HRQE1 and HRQE0 are
DSP56012 User's Manual
2
C master
MOTOROLA
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