Motorola DSP56012 User Manual page 265

A
Address Buses 1-12
Address Generation Unit 1-11
AES/EBU 8-3
B
bootstrap loading using the HI 4-54
Bootstrap Program Listing A-4
bootstrap ROM 1-16
Bootstrap ROM — See Appendix A
C
,
CDP Format 1-19 6-3
Clock 2-7
Command Vector Register (CVR) 4-29
CP-340 8-3
CPHA and CPOL (HCKR Clock Phase and
Polarity Controls) 5-10
CVR register 4-29
bit 0–5—Host Vector bits (HV) 4-29
bit 6—reserved 4-30
bit 7—Host Command bit (HC) 4-30
D
Data ALU 1-11
Data Buses 1-12
data transfer
DMA 4-59
,
DSP to host 4-19 4-56
,
host to DSP 4-18 4-49
polling/interrupt controlled 4-45
DAX
Block Transferred Interrupt Handling 8-14
Initiating A Transmit Session 8-14
Transmit Register Empty Interrupt
Handling 8-14
DAX Audio Data register Empty (XADE) status
flag 8-10
DAX Audio Data Registers (XADRA/XADRB) 8-7
DAX Audio Data Shift Register (XADSR) 8-8
DAX biphase encoder 8-12
DAX Block transfer (XBLK) flag 8-11
DAX Channel A Channel status (XCA) bit 8-9
DAX Channel A User data (XUA) bit 8-9
Motorola
Index
DAX Channel A Validity (XVA) bit 8-9
DAX Channel B Channel Status (XCB) bit 8-10
DAX Channel B User Data (XUB) bit 8-10
DAX Channel B Validity (XVB) bit 8-9
DAX Clock input Select bits 8-9
DAX clock multiplexer 8-13
DAX clock selection 8-9
DAX Control Register (XCTR) 8-8
DAX Enable (XEN) bit 8-8
DAX internal architecture 8-6
DAX Interrupt Enable (XIEN) bit 8-8
DAX Non-Audio Data Buffer (XNADBUF) 8-12
DAX Operation During Stop 8-15
DAX Parity Generator (PRTYG) 8-12
DAX preamble generator 8-12
DAX Preamble sequence 8-13
DAX Programming Considerations 8-14
DAX programming model 8-6
DAX Status Register (XSTR) 8-10
DAX Stop control (XSTP) bit 8-8
DAX Transmit In Progress (XTIP) status flag 8-11
DAX Transmit Underrun error (XAUR) status
flag 8-10
Digital Audio Transmitter (DAX) 8-3
,
DMA bit 4-18
DMA mode 4-26
DMA procedure
DSP to host 4-65
host to DSP 4-62
DMA Status bit (DMA) 4-18
DSP to host
DMA procedure 4-65
internal processing 4-64
DSP56011 Features 1-6
F
Frequency Multiplication by the PLL 1-12
G
GC0-GC3 (GPIOR Control Bits) 7-4
GD0-GD3 (GPIOR Data Bits) 7-4
GDD0-GDD3 (GPIOR Data Direction Bits) 7-4
General Purpose I/O — See Section 7
General Purpose I/O (GPIO) 1-19
General Purpose Input/Output (GPIO) 1-10
GPIO
4-32
,
4-32
I-1