Servicing Dma Interrupts; Figure 4-17 Dma Transfer Logic And Timing - Motorola DSP56012 User Manual

DSP56012
HOREQ
+5 V
HACK
REQ0
8T
High
Byte
HACK
1 DMA Cycle = 8T = 4 DMA Clock Cycles
Max. MC68440 Clock = 10 MHz = > T = 50 ns
4.4.7.5

Servicing DMA Interrupts

When HM0 0 and/or HM1
transfer. Generally the HOREQ pin will be connected to the REQ input of a DMA
controller. The HOA[2:0], HR/W, and HEN pins are not used during DMA transfers;
DMA transfers only use the HOREQ and HACK pins after the DMA channel has
been initialized. HACK is used to strobe the data transfer, as shown in Figure 4-17
on page 4-41 where an MC68440 is used as the DMA controller. DMA transfers to
and from the HI are presented in more detail in Section 4.4.8 Host Interface
Application Examples.
MOTOROLA
+5 V
CI
D
Q
Middle
Byte

Figure 4-17 DMA Transfer Logic and Timing

0, HOREQ will be asserted to request a DMA
DSP56012 User's Manual
To IRQB
Burst
To Transfer 24-bit Word
Low
Byte
DMA ACK Gated Off
Parallel Host Interface
Host Interface (HI)
IRQ
+5 V
REQ0
MC68440
ACK0
A0
A1
AS
OWN
Fast Interrupt
High
Byte
AA0325k
4-41