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4.4.4.2.3
HSR HI Command Pending (HCP)—Bit 2
The HI Command Pending (HCP) bit indicates that the host has set the HC bit and
that a host command interrupt is pending. The HCP bit reflects the status of the Host
Command (HC) bit in the Command Vector Register (CVR). HC and HCP are cleared
by the DSP interrupt hardware when the interrupt is taken. The host can clear HC,
which also clears HCP.
Note: Hardware reset, software reset, individual reset, and Stop mode clear HCP.
4.4.4.2.4
HSR HI Flag 0 (HF0)—Bit 3
The HI Flag 0 (HF0) bit in the HSR indicates the state of Host Flag 0 in the ICR (on the
host processor side). HF0 in HSR can only be changed by the host processor (see
Figure 4-9).
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF0.
4.4.4.2.5
HSR HI Flag 1 (HF1)—Bit 4
The HI Flag 1 (HF1) bit in the HSR indicates the state of host flag 1 in the ICR (on the
host processor side). HF1 can only be changed by the host processor (see Figure 4-9).
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF1.
MOTOROLA
DSP56012 User's Manual
Parallel Host Interface
Host Interface (HI)
4-17
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