Polling/Interrupt Controlled Data Transfer; Figure 4-21 Hi Mode And Init Bits - Motorola DSP56012 User Manual

7
Host Sets
INIT
INIT Bit
Interrupt Mode (DMA Off)
TREQ RREQ
0 0 INIT = 0; Address Counter = 00
0 1 INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = 00
1 0 INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = 00
1 1 INIT = 0; RXDF = 0; HTDE = 1: TXDE = 1;
HRDF = 0; Address Counter = 00
INIT is used by the host to force initialization of the HI hardware.
The HI hardware automatically clears INIT when the command is executed.
INIT is cleared by DSP RESET.
4.4.8.2

Polling/Interrupt Controlled Data Transfer

Handshake flags are provided for polled or interrupt-driven data transfers. Because
the DSP interrupt response is sufficiently fast, most host microprocessors can load or
store data at their maximum programmed I/O (non-DMA) instruction rate without
testing the handshake flags for each transfer. If the full handshake is not needed, the
host processor can treat the DSP as fast memory, and data can be transferred between
the host and DSP at the fastest host processor rate. DMA hardware can be used with
the external host request and host acknowledge pins to transfer data at the maximum
DSP interrupt rate.
MOTOROLA
Modes
6 5 4
HM1 HM0 HF1 HF0
0 0 Interrupt Mode (DMA Off)
0 1 24-Bit DMA Mode
1 0 16-Bit DMA Mode
1 1 8-Bit DMA Mode
INIT Execution

Figure 4-21 HI Mode and INIT Bits

DSP56012 User's Manual
3 2 1 0
HF00 TREQ RREQ
DMA Mode
TREQ RREQ
0 0 INIT = 0; Address Counter = HM1, HM0
0 1 INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = HM1, HM0
1 0 INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = HM1, HM0
1 1 Undefined (Illegal)
Parallel Host Interface
Host Interface (HI)
Interrupt Control Register
(ICR)
(Read/Write)
Reset Condition
INIT Execution
AA0329k
4-45