Table of Contents
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L
Low Power Divider 1-12
M
Manual Conventions 1-5
,
MEC Format 1-19
6-3
Memories 1-13
Memory — See Section 3
Memory Maps 1-17
MF0-MF11 (PLL Multiplication Factor) 3-19
MODB/IRQB 2-8
mode control 2-8
Mode Select A/External Interrupt Request A 2-8
Mode Select B/External Interrupt Request B 2-8
2-9
Multiplication Factor 3-19
O
On-Chip Emulation (OnCE) Port 1-13
On-chip Peripherals Memory Map 1-17
Operating Modes — See Section 3
P
Parallel Host Interface 1-10
PBC register 4-3
Peripheral Memory Map 1-17
Phase Lock Loop (PLL) 1-12
PLL 2-7
PLL (Phase Lock Loop)
Multiplication Factor (MF) 3-19
PM0-PM7 (BRC Prescale Modulus Select) 6-10
polling 4-38
Port B
pin control logic 4-7
Port B Control register (PBC) 4-3
Program Control Unit 1-12
Program Memory 1-13
Programming
SAI Considerations 6-24
Transmitter Clock Polarity (TCKP) 6-20
Transmitter Data Shift Direction (TDIR) 6-19
Transmitter Data Word Expansion
(TDWE) 6-21
Transmitter Left Right Selection (TLRS) 6-19
Programming Model
GPIO 7-3
SAI 6-8
SHI—DSP Side 5-6
SHI—Host Side 5-5
programming model
I-4
,
,
B-4
,
B-4
,
HI 4-13
4-21
Programming Reference — See Appendix B
PSR (BRC Prescaler Range) 6-10
R
R0EN (RCS Receiver 0 Enable) 6-10
R1EN (RCS Receiver 1 Enable) 6-11
RCKP (RCS Receiver Clock Polarity) 6-13
RCS (Receiver Control/Status Register) 6-10
RDIR (RCS Receiver Data Shift Direction) 6-12
RDWT (RCS Receiver Data Word Truncation) 6-14
Receive Byte registers (RXH, RXM, RXL) 4-32
Receive Data Register Full bit (RXDF) 4-30
Receive Request Enable bit (RREQ) 4-24
reserved bit
in CVR register 4-30
in HCR register 4-16
in HSR register 4-18
in ISR register 4-31
RESET 2-9
Reset 2-9
reset
HI register contents 4-19
RLDF (RCS Receiver Left Data Full) 6-16
RLRS (RCS Receiver Left Right Selection) 6-12
RMST (RCS Receiver Master) 6-11
RRDF (RCS Receiver Right Data Full) 6-16
RREQ bit 4-24
RWL0-RWL1 (RCS Receiver Word Length
Control) 6-11
RX0 and RX1 (Receive Data Registers) 6-17
RXDF bit 4-30
RXH register 4-32
RXIE (RCS Receiver Interrupt Enable) 6-15
RXIL (RCS Receiver Interrupt Location) 6-15
RXL register 4-32
RXM register 4-32
S
SAI 6-3
Baud Rate Control Register (BRC) 6-9
Baud Rate Generator 6-4
BRC
Prescale Modulus Select 6-10
Prescaler Range 6-10
Reserved Bits 6-10
Initiating A Transmit Session 6-24
Internal Architecture 6-4
Internal Interrupt Priorities 6-9
Operation During Stop 6-24
Operation Under Irregular Conditions 6-25
Programming Considerations 6-24
Motorola
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