Figure 4-15 Interrupt Vector Register Read Timing; Figure 4-16 Hi Interrupt Structure - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
7
$3
MC68000
1. The DSP56012 Asserts HOREQ to interrupt the host
processor.
IPL2
IPL1
IPL0
2. The host processor asserts HACK with its interrupt
acknowledge cycle.
A1–A31
FC0–FC2
AS
3. When HOREQ and HACK are asserted simultaneously,
the contents of the IVR are placed on the host data bus.
D0–D7

Figure 4-15 Interrupt Vector Register Read Timing

7
DMA 0
$2 HOREQ
HOREQ Asserted
7
$3 INIT HM1 HM0
4-40
Interrupt Vector Number
IACK
IACK
LOGIC
HF3 HF2 TRDY TXDE RXDF
HF1 HF0 0

Figure 4-16 HI Interrupt Structure

DSP56012 User's Manual
0
Interrupt Vector Register (IVR)
(Read/Write)
Status
0
interrupt Source
ISR
0
TREQ RREQ
ICR
Mask
+5 V
DSP56012
1 K
HOREQ
HACK
Interrupt
Vector
$0F
Register
(IVR)
H0–H7
HOREQ
MOTOROLA
AA0323.11
AA0324k