Figure B-1 On-Chip Peripheral Memory Map - Motorola DSP56012 User Manual

Programming Reference
23
X:$FFFF
X:$FFFE
X:$FFFD
X:$FFFC
X:$FFFB
X:$FFFA
X:$FFF9
X:$FFF8
X:$FFF7
X:$FFF6
X:$FFF5
X:$FFF4
X:$FFF3
X:$FFF2
X:$FFF1
X:$FFF0
X:$FFEF
X:$FFEE
X:$FFED
X:$FFEC
X:$FFEB
X:$FFEA
X:$FFE9
X:$FFE8
X:$FFE7
X:$FFE6
X:$FFE5
X:$FFE4
X:$FFE3
X:$FFE2
X:$FFE1
X:$FFE0
X:$FFDF
X:$FFDE
X:$FFDD
X:$FFDC
X:$FFDB
X:$FFDA
X:$FFD9
X:$FFD8
X:$FFD7
X:$FFD6
X:$FFD5
X:$FFD4
X:$FFD3
X:$FFC0
= Unused and reserved; read as a random number; should not be written, to ensure future compatibility
= Unused and reserved; consult the appropriate chapter for information on how to ensure future compatibility
B-4
16 15 8 7

Figure B-1 On-chip Peripheral Memory Map

DSP56012 User's Manual
0
Interrupt Priority Register (IPR)
Reserved
PLL Control Register (PCTL)
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO Control/Data Register (GPIOR)
Reserved
Reserved
Reserved
SHI Receive FIFO/Transmit Register (HRX/HTX)
2
SHI I C Slave Address Register (HSAR)
SHI Host Control/Status Register (HCSR)
SHI Host Clock Control Register (HCKR)
Reserved
Port B Data Register (PBD)
Port B Data Direction Register (PBDDR)
Port B Control Register (PBC)
HI Receive/Transmit Register (HORX/HOTX)
Reserved
Host Interface Status Register (HSR)
Host Interface Control Register (HCR)
SAI TX2 Data Register (TX2)
SAI TX1 Data Register (TX1)
SAI TX0 Data Register (TX0)
SAI TX Control/Status Register (TCS)
SAI RX1 Data Register (RX1)
SAI RX0 Data Register (RX0)
SAI RX Control/Status Register (RCS)
SAI Baud Rate Control Register (BRC)
DAX Status Register (XSTR)
DAX Control Register (XCTR)
Reserved
DAX Transmit Data Registers (XADRA/XADRB)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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