Serial Host Interface Internal Architecture; Figure 5-1 Serial Host Interface Block Diagram - Motorola DSP56012 User Manual

Serial Host Interface

Serial Host Interface Internal Architecture

5.2

SERIAL HOST INTERFACE INTERNAL ARCHITECTURE

The DSP views the SHI as a memory-mapped peripheral in the X data memory space.
The DSP may use the SHI as a normal memory-mapped peripheral using standard
polling or interrupt programming techniques. Memory mapping allows DSP
communication with the SHI registers to be accomplished using standard
instructions and addressing modes. In addition, the MOVEP instruction allows
interface-to-memory and memory-to-interface data transfers without going through
an intermediate register. The single master configuration allows the DSP to directly
connect to dumb peripheral devices. For that purpose, a programmable baud-rate
generator is included to generate the clock signal for serial transfers. The host side
invokes the SHI, for communication and data transfer with the DSP, through a shift
register that may be accessed serially using either the I
Figure 5-1 shows the SHI block diagram.
Host Accessible
SCK/SCL
MISO/SDA
MOSI/HA0
Pin
Control
Logic
SS/HA2
HREQ

Figure 5-1 Serial Host Interface Block Diagram

5-4
Clock
Generator
Controller
Logic
INPUT/OUTPUT Shift Register
Slave
Address
Recognition
Unit
(SAR)
DSP56012 User's Manual
2
C or the SPI bus protocols.
DSP Accessible
HCKR
HCSR
HTX
(IOSR)
HRX
(FIFO)
HSAR
24 BIT
DSP
Global
Data
Bus
AA0416
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