Phase Lock Loop (Pll); Table 2-4 Phase Lock Loop Signals - Motorola DSP56012 User Manual

2.4

PHASE LOCK LOOP (PLL)

Signal Name Type
PLOCK Output
PCAP Input
PINIT Input
EXTAL Input
MOTOROLA

Table 2-4 Phase Lock Loop Signals

State During
Reset
Indeterminate Phase Locked—PLOCK is an output signal that, when
driven high, indicates that the PLL has achieved phase
lock. After Reset, PLOCK is driven low until lock is
achieved.
Note:
Input PLL Capacitor—PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor
terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP may be tied to V
or left floating.
Input PLL Initial—During assertion of RESET, the value of
PINIT is written into the PLL Enable (PEN) bit of the PLL
Control Register, determining whether the PLL is
enabled or disabled.
Input External Clock/Crystal Input—EXTAL interfaces the
internal crystal oscillator input to an external crystal or
an external clock.
DSP56012 User's Manual

Phase Lock Loop (PLL)

Signal Description
PLOCK is a reliable indicator of the PLL lock
state only after the chip has exited the Reset
state. During hardware reset, the PLOCK state is
determined by PINIT and the current PLL lock
condition.
Signal Descriptions
.
CCP
, GND,
CC
2-7