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15
Transmit Control/Status (TCS)
TCLOCK
Transmit Controller
Figure 6-3 SAI Transmit Section Block Diagram
The transmitter section data path consists of three fully synchronized sets of data and
shift registers capable of operating simultaneously. In each set, the 24-bit shift
register contains the data being transmitted. Data is shifted out to the associated SDO
pin at the transitions of the serial transmit clock SCKT. Data is shifted out MSB first if
TDIR is cleared, and LSB first if TDIR is set. The number of bits shifted out before the
shift register is considered empty and ready to be reloaded can be 16, 24, or 32 bits as
determined by the TWL1 and TWL0 control bits in the TCS register. A special control
mechanism is used to emulate a 32-bit shift register if the word length is defined as 32
bits. This is done by enabling eight data shifts at the beginning/end of the data word
transfer, according to the TDWE bit in the TCS register. These shift registers cannot
be directly accessed by the DSP.
MOTOROLA
Serial Audio Interface Internal Architecture
Global Data Bus (GDB)
0
Status
Control
.
DSP56012 User's Manual
Serial Audio Interface
23
TX0 Data Register
23
TX0 Shift Register
23
TX1 Data Register
23
TX1 Shift Register
23
TX2 Data Register
23
TX2 Shift Register
0
0
SDO0
0
0
SDO1
0
0
SDO2
AA0429k
6-7
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