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2.7
SERIAL HOST INTERFACE (SHI)
The SHI has five I/O signals that can be configured to allow the SHI to operate in
either SPI or I
Signal
Signal
Name
Type
SCK/
Input or
SCL
Output
MOTOROLA
2
C mode.
Table 2-7 Serial Host Interface (SHI) Signals
State
during
Reset
Tri-stated
SPI Serial Clock/I
output when the SPI is configured as a master, and a
Schmitt-trigger input when the SPI is configured as a slave.
When the SPI is configured as a master, the SCK signal is
derived from the internal SHI clock generator. When the SPI
is configured as a slave, the SCK signal is an input, and the
clock signal from the external master synchronizes the data
transfer. The SCK signal is ignored by the SPI if it is defined
as a slave and the Slave Select (SS) signal is not asserted. In
both the master and slave SPI devices, data is shifted on one
edge of the SCK signal and is sampled on the opposite edge
where data is stable. Edge polarity is determined by the SPI
transfer protocol. SCL carries the clock for I
transactions in the I
when configured as a slave, and an open-drain output when
configured as a master. SCL should be connected to V
through a pull-up resistor.
The maximum allowed internally generated bit clock
frequency is f
mode where f
allowed externally generated bit clock frequency is f
the SPI mode and f
An external pull-up resistor is not required.
DSP56012 User's Manual
Serial Host Interface (SHI)
Signal Description
2
C Serial Clock—The SCK signal is an
2
C mode. SCL is a Schmitt-trigger input
/4 for the SPI mode and f
osc
is the clock on EXTAL. The maximum
osc
2
/5 for the I
C mode
osc
Signal Descriptions
2
C bus
CC
2
/6 for the I
C
osc
/3 for
osc
2-13
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