Quectel 5G Series Hardware Design
  1. Manuals
  2. Brands
  3. Quectel Manuals
  4. Control Unit
  5. 5G Module Series
  6. Hardware design
Quectel 5G Series Hardware Design

Quectel 5G Series Hardware Design

Hide thumbs Also See for 5G Series:
Table of Contents

Advertisement

Quick Links

RM500Q-GL
Hardware Design
5G Module Series
Version: 1.1
Date: 2021-03-10
Status: Released
www.quectel.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the 5G Series and is the answer not in the manual?

Questions and answers

Related Manuals for Quectel 5G Series

Summary of Contents for Quectel 5G Series

  • Page 1 RM500Q-GL Hardware Design 5G Module Series Version: 1.1 Date: 2021-03-10 Status: Released www.quectel.com...
  • Page 2 To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable.
  • Page 3 RM500Q-GL Hardware Design Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design.

  • Page 4: Safety Information

    Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 5: About The Document

    5G Module Series RM500Q-GL Hardware Design About the Document Revision History Version Date Author Description Norton ZHANG/ 2020-08-31 Kingson ZHANG Initial Qiqi WANG 1. Updated the status of 5G NR SA bands (in Table 2); 2. Added the supported GNSS system: GZSS (in Table 2); 3.

  • Page 6: Table Of Contents

    5G Module Series RM500Q-GL Hardware Design Contents Safety Information ............................3 About the Document ........................... 4 Contents ............................... 5 Table Index ..............................8 Figure Index ............................... 10 Introduction ............................11 1.1. Introduction ..........................11 1.2. Reference Standard ........................11 1.3. Special Mark ..........................
  • Page 7 5G Module Series RM500Q-GL Hardware Design 4.3. PCIe Interface ........................... 42 4.3.1. PCIe Operating Mode ....................42 4.3.2. Pin Definition of PCIe ..................... 43 4.3.3. Reference design for PCIe ..................... 44 4.3.4. PCIe Timing ........................45 4.4. PCM Interface ........................... 47 4.5.
  • Page 8 5G Module Series RM500Q-GL Hardware Design 6.7. Operating and Storage Temperatures ..................78 Mechanical Dimensions and Packaging ..................79 7.1. Mechanical Dimensions of the Module ..................79 7.2. Top and Bottom Views of the Module ..................80 7.3. M.2 Connector ........................... 80 7.4.
  • Page 9 5G Module Series RM500Q-GL Hardware Design Table Index Table 1: Special Mark..........................12 Table 2: Frequency Bands and GNSS Systems of RM500Q-GL Module ..........13 Table 3: Key Features of RM500Q-GL ...................... 14 Table 4: Definition of I/O Parameters ......................19 Table 5: Pin Description ..........................
  • Page 10 5G Module Series RM500Q-GL Hardware Design Table 42: (U)SIM 1.8 V I/O Requirements ....................75 Table 43: (U)SIM 3.0V I/O Requirements ....................76 Table 44: Electrostatic Discharge Characteristics (Temperature: 25 º C, Humidity: 40 %) ....... 76 Table 45: Absolute Maximum Ratings ....................... 78 Table 46: Operating and Storage Temperatures ..................
  • Page 11 5G Module Series RM500Q-GL Hardware Design Figure Index Figure 1: Functional Block Diagram ......................17 Figure 2: Pin Assignment ........................... 18 Figure 3: DRX Run Time and Current Consumption in Sleep Mode ............25 Figure 4: Sleep Mode Application with USB Remote Wakeup ..............25 Figure 5: Power Supply Limits During Radio Transmission ..............

  • Page 12: Introduction

    5G Module Series RM500Q-GL Hardware Design Introduction 1.1. Introduction This document introduces RM500Q-GL module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of the module.

  • Page 13: Special Mark

    5G Module Series RM500Q-GL Hardware Design 1.3. Special Mark Table 1: Special Mark Mark Definition When an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin name, AT command, or argument is under development and currently not supported, unless otherwise specified.

  • Page 14: Product Concept

    5G Module Series RM500Q-GL Hardware Design Product Concept 2.1. General Description RM500Q-GL is a 5G NR/LTE-FDD/LTE-TDD/UMTS/HSPA+ wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks. RM500Q-GL is standard M.2 Key-B WWAN module. For more details, see PCI Express M.2 Specification Revision 3.0, Version 1.2.

  • Page 15: Key Features

    5G Module Series RM500Q-GL Hardware Design RM500Q-GL can be applied in the following fields: ⚫ Rugged tablet PC and laptop computer ⚫ Remote monitor system ⚫ Smart metering system ⚫ Wireless CPE ⚫ Smart TV ⚫ Outdoor Live devices ⚫ Wireless router and switch ⚫...
  • Page 16 5G Module Series RM500Q-GL Hardware Design synchronization ⚫ WCDMA bands: Class 3 (24 dBm +1/-3 dB) ⚫ LTE bands: Class 3 (23 dBm ± 2 dB) Transmitting ⚫ LTE B38/B40/B41/B42/B43 bands HPUE : Class 2 (26 dBm ± 2 dB) Power ⚫...
  • Page 17 RM500Q-GL Hardware Design Interfaces ⚫ Compliant with 3GPP TS 27.007 and 3GPP TS 27.005 AT Commands ⚫ Quectel enhanced AT commands ⚫ Internet Protocol Supports QMI/NTP* protocols ⚫ Features Supports the protocols PAP and CHAP usually used for PPP connections ⚫...

  • Page 18: Evaluation Board

    RM500Q-GL Hardware Design 2.3. Evaluation Board To help you develop applications conveniently with RM500Q-GL, Quectel supplies an evaluation board (PCIe Card EVB), a USB to RS-232 converter cable, a USB type-B cable, antennas and other peripherals to control or test the module. For more details, see document [3].

  • Page 19: Pin Assignment

    5G Module Series RM500Q-GL Hardware Design 2.5. Pin Assignment The following figure shows the pin assignment of RM500Q-GL. The top side contains the four antenna connectors. Pin Name Pin Name CONFIG_2 CONFIG_1 AP2SDX_STATUS RESET# USIM1_DET RFFE_VIO_1V8 COEX_TXD PIN75 PIN74 ANTCTL2 COEX_RXD ANTCTL1 WLAN_TX_EN...

  • Page 20: Pin Description

    5G Module Series RM500Q-GL Hardware Design 2.6. Pin Description Table 4: Definition of I/O Parameters Type Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Pull Up Pull Down The following table shows the pin definition and description of RM500Q-GL. Table 5: Pin Description Pin Name Description...
  • Page 21 5G Module Series RM500Q-GL Hardware Design Ground Turn on/off of the max = 4.4 V Internally pulled FULL_CARD_ module. min = 1.19 V down with a 100 POWER_OFF# High level: Turn on max = 0.2 V kΩ resistor Low level: Turn off USB 2.0 differential USB_DP data (+)
  • Page 22 5G Module Series RM500Q-GL Hardware Design GNSS disable control. W_DISABLE2# DI, OD 1.8/3.3 V Active LOW Ground PCM_SYNC DIO, PD PCM data frame sync 1.8 V USB 3.1 super-speed USB_SS_TX_M transmit (-) USIM1_VDD USIM1_RST DO, PD (U)SIM1 card reset 1.8/3.0 V USB 3.1 super-speed USB_SS_TX_P transmit (+)
  • Page 23 5G Module Series RM500Q-GL Hardware Design (U)SIM2 card 1.8/3.0 V PCIE_RX_P PCIe receive (+) PCIe reset. PCIE_RST_N DI, OD Active LOW Ground PCIe clock request. PCIE_CLKREQ_N DO, OD Active LOW. PCIE_REFCLK_M AI, AO PCIe reference clock (-) PCIe wake up. PCIE_WAKE_N DO, OD Active LOW...
  • Page 24 This pin is pulled LOW by default, and will be internally pulled up to 1.8 V by software configuration 、 only when (U)SIM hot-plug is enabled by AT+QSIMDET. If this function is required, please contact Quectel for more details. 3. Keep all NC, reserved and unused pins unconnected. RM500Q-GL_Hardware_Design...

  • Page 25: Operating Characteristics

    5G Module Series RM500Q-GL Hardware Design Operating Characteristics 3.1. Operating Modes The table below briefly summarizes the various operating modes to be mentioned in the following chapters. Table 6: Overview of Operating Modes Mode Details Software is active. The module has registered on the network, and it Idle is ready to send and receive data.
  • Page 26 5G Module Series RM500Q-GL Hardware Design DRX OFF Run Time Figure 3: DRX Run Time and Current Consumption in Sleep Mode The following part of this section presents the power saving procedure and sleep mode of the module. If the host supports USB suspend/resume and remote wakeup function, the following two conditions must be met to make the module enter sleep mode.

  • Page 27: Airplane Mode

    5G Module Series RM500Q-GL Hardware Design 3.1.2. Airplane Mode The module provides a W_DISABLE1# pin to disable or enable the airplane mode through hardware operation. See Chapter 4.5.1 for more details. 3.2. Communication Interface with a Host The module supports to communicate through both USB and PCIe interfaces, respectively referring to the USB mode and the PCIe mode as described below: USB Mode ⚫...

  • Page 28: Power Supply

    5G Module Series RM500Q-GL Hardware Design 3.3. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 7: Definition of VCC and GND Pins Pin No. Pin Name Description DC Characteristics 3.135–4.4 V 2, 4, 70, 72, 74 Power Supply 3.7 V typical DC supply 3, 5, 11, 27, 33, 39, 45,...

  • Page 29: Reference Design For Power Supply

    5G Module Series RM500Q-GL Hardware Design Module VCC (3.7 V Typ.) 2, 4 220 μF 1 μF 100 nF 33 pF 10 pF 3, 5, 11 70, 72, 74 220 μF 1 μF 5.1 V 100 nF 33 pF 10 pF 27, 33, 39, 45, 51, 57, 71, 73...

  • Page 30: Monitor The Power Supply

    5G Module Series RM500Q-GL Hardware Design NOTE To avoid damages to the internal flash, DON'T cut off the power supply before the module is completely turned off by pulling down FULL_CARD_POWER_OFF# pin for more than 7 s, and DON'T cut off power supply directly when the module is working.
  • Page 31 5G Module Series RM500Q-GL Hardware Design It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit is illustrated by the following figure. Host Module 1.8 V or 3.3 V FULL_CARD_POWER_OFF# GPIO 100k NOTE: The voltage of pin 6 should be no less than 1.19 V when it is at high level. Figure 8: Turn on the Module with a Host GPIO The timing of turn-on scenario is illustrated by the following figure.

  • Page 32: Turn Off

    5G Module Series RM500Q-GL Hardware Design Table 9: Turn-on Timing of the Module Symbol Min. Typ. Max. Comment 0 ms 20 ms Module power-on time depending on the host. power-on Time period between module power-on and 33 ms VCC-RST# RESET# being driven HIGH. 68 ms Module system turn-on time.

  • Page 33: Turn Off The Module Through At Command

    5G Module Series RM500Q-GL Hardware Design Table 10: Turn-off Timing of the Module Through FCPO# Symbol Min. Typ. Max. Comment 6.84s Module system turn-off time. turn-off 3.5.2. Turn off the Module Through AT Command It is also a safe method to turn off the module by AT+QPOWD command. For more details about the command, see document [4].

  • Page 34: Reset The Module

    5G Module Series RM500Q-GL Hardware Design 3.6. Reset the Module RESET# is an asynchronous and active LOW signal (1.8 V logic level). Whenever this pin is active, the module will immediately enter Power On Reset (POR) condition. Please note that triggering the RESET# signal will lead to loss of all data in the modem and removal of system drivers.
  • Page 35 5G Module Series RM500Q-GL Hardware Design Module VDD 1.8V 100k RESET# Reset Logic 33 pF 200-980 ms NOTE: The capacitor C1 is recommended to be less than 47 pF. Figure 13: Reference Circuit of RESET# with Button The reset timing is illustrated by the following figure. 3.7 V VCC(H) 1.8 V...

  • Page 36: Application Interfaces

    5G Module Series RM500Q-GL Hardware Design Application Interfaces The physical connections and signal levels of RM500Q-GL comply with PCI Express M.2 specification. This chapter mainly describes the definition and application of the following interfaces/pins of the module: ⚫ (U)SIM interfaces ⚫...

  • Page 37: U)Sim Hot-Plug

    5G Module Series RM500Q-GL Hardware Design USIM1_DET DI, PU (U)SIM1 card hot-plug detection. 1.8 V USIM2_VDD USIM2_VDD Power supply for (U)SIM2 card 1.8/3.0 V USIM2_VDD USIM2_DATA DIO, PU (U)SIM2 card data 1.8/3.0 V USIM2_VDD USIM2_CLK DO, PD (U)SIM2 card clock 1.8/3.0 V USIM2_VDD USIM2_RST...

  • Page 38: Normally Closed (U)Sim Card Connector

    5G Module Series RM500Q-GL Hardware Design The command takes effect after the module is restarted. Characteristics The configuration will be saved automatically. Parameter <enable> Integer type. Enable or disable (U)SIM card detection. Disable Enable <insert_level> Integer type. The level of (U)SIM detection pin when a (U)SIM card is inserted. Low level High level NOTES...

  • Page 39: Normally Open (U)Sim Card Connector

    5G Module Series RM500Q-GL Hardware Design The following figure shows a reference design for (U)SIM interface with a normally closed (U)SIM card connector. USIM_VDD Module (U)SIM Card Connector 100 nF 10-20k USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA NOTE: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. Figure 15: Reference Circuit for Normally Closed (U)SIM Card Connector 4.1.4.

  • Page 40: U)Sim Card Connector Without Hot-Plug

    5G Module Series RM500Q-GL Hardware Design The following figure shows a reference design for (U)SIM interface with a normally open (NO) (U)SIM card connector. USIM_VDD Module (U)SIM Card Connector 100 nF 10-20k USIM_VDD USIM_RST USIM_CLK USIM_DET 0 Ω USIM_DATA NOTE: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.

  • Page 41: U)Sim Design Notices

    5G Module Series RM500Q-GL Hardware Design 4.1.6. (U)SIM Design Notices To enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. ⚫ Place the (U)SIM card connector as close to the module as possible. Keep the trace length less than 200 mm.
  • Page 42 5G Module Series RM500Q-GL Hardware Design USB_SS_RX_P USB 3.1 super-speed receive (+) For more details about the USB 3.1 & 2.0 specifications, please visit http://www.usb.org/home. The USB 2.0 interface is recommended to be reserved for firmware upgrade in designs. The following figure shows a reference circuit for USB 2.0/3.1 interface.

  • Page 43: Pcie Interface

    5G Module Series RM500Q-GL Hardware Design should pay attention to the selection of the device. Typically, the stray capacitance should be less than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1. ⚫ Keep the ESD protection devices as close to the USB connector as possible. ⚫...

  • Page 44: Pin Definition Of Pcie

    5G Module Series RM500Q-GL Hardware Design NOTES The underlined value is the default parameter value. For more details about the command, see document [4]. 4.3.2. Pin Definition of PCIe The following table shows the pin definition of PCIe interface. Table 16: Pin Definition of PCIe Interface Pin No.

  • Page 45: Reference Design For Pcie

    5G Module Series RM500Q-GL Hardware Design 4.3.3. Reference design for PCIe The following figure shows a reference circuit for the PCIe interface. Host Module PCIE_REFCLK_P R4 0Ω PCIE_REFCLK_P PCIE_REFCLK_M R5 0Ω PCIE_REFCLK_M PCIE_RX_P C3 220 nF PCIE_TX_P PCIE_RX_M C4 220 nF PCIE_TX_M PCIE_TX_P C1 220 nF...

  • Page 46: Pcie Timing

    5G Module Series RM500Q-GL Hardware Design 4.3.4. PCIe Timing The following figure is PCIe power-up timing sequence for an adapter powered from system power rail in PCI Express M.2 specification. Figure 20: PCIe Power-on Timing Requirements of M.2 Specification The following table is power-up timing variables in PCI Express M.2 specification. Table 17: Power-up Timing of M.2 Specification Symbol Min.
  • Page 47 5G Module Series RM500Q-GL Hardware Design The following figure and table are PCIe turn-on timing and variables of the module. Module power-on or insertion detection 3.7 V ≥ 1.19 V System turn-on and booting FCPO# 1.8 V VCC-RST# RESET# 1.8 V RFFE_VIO_1V8 >...

  • Page 48: Pcm Interface

    5G Module Series RM500Q-GL Hardware Design 4.4. PCM Interface RM500Q-GL supports audio communication via Pulse Code Modulation (PCM) digital interface. The PCM interface supports the following modes: ⚫ Primary mode (short frame synchronization): the module works as both master and slave ⚫...
  • Page 49 5G Module Series RM500Q-GL Hardware Design 125 μs PCM_CLK PCM_SYNC PCM_DOUT PCM_DIN Figure 23: Auxiliary Mode Timing The following table shows the pin definition of PCM interface which can be applied to audio codec design. Table 19: Pin Definition of PCM Interface Pin No.

  • Page 50: Control And Indication Interfaces

    5G Module Series RM500Q-GL Hardware Design 4.5. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 20: Pin Definition of Control and Indication Interfaces Pin No. Pin Name Description DC Characteristic Airplane mode control. W_DISABLE1# DI, OD 1.8/3.3 V...

  • Page 51: W_Disable2

    5G Module Series RM500Q-GL Hardware Design AT+CFUN=0 AT+CFUN=1 Disabled AT+CFUN=4 4.5.2. W_DISABLE2# RM500Q-GL provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2# pin is pulled up by default. Driving it low will disable the GNSS function. The combination of W_DISABLE2# pin and AT commands controls the GNSS function.

  • Page 52: Wwan_Led

    5G Module Series RM500Q-GL Hardware Design 4.5.3. WWAN_LED# WWAN_LED# is used to indicate the RF status of the module, and its sink current is up to 10 mA. To reduce current consumption of the LED, a current-limited resistor must be placed in series with the LED, as illustrated by the figure below.

  • Page 53: Dpr

    5G Module Series RM500Q-GL Hardware Design The module operation status indicated by WAKE_ON_WAN# is shown as below. Table 24: State of WAKE_ON_WAN# WAKE_ON_WAN# State Module Operation Status Output a one-second pulse signal at low level Call/SMS/Data is incoming (to wake up the host) Always at high voltage level Idle/Sleep Host...

  • Page 54: Status

    5G Module Series RM500Q-GL Hardware Design 4.5.6. STATUS* RM500Q-GL provides two status indication pins for communication with IPQ807x device. Pin 38 (SDX2AP_STATUS) outputs the status indication signal to IPQ807x device, and pin 68 (AP2SDX_STATUS) inputs the status indication signal from IPQ807x device. For more details, see document [5].

  • Page 55: Configuration Pins

    Antenna Control ANTCTL2* DO, PD 1.8 V NOTE If this function is required, please contact Quectel for more details. 4.8. Configuration Pins RM500Q-GL provides four configuration pins, which are defined as below. Table 28: Configuration Pins List of M.2 Specification Config_0...
  • Page 56 5G Module Series RM500Q-GL Hardware Design The following figure shows a reference circuit for these four pins. Host Module VCC_IO_HOST NM-0Ω CONFIG_0 GPIO 0Ω CONFIG_1 GPIO NM-0Ω CONFIG_2 GPIO CONFIG_3 NM-0Ω GPIO NOTE: The voltage level of VCC_IO_HOST depends on the host side and could be 1.8 V or 3.3 V. Figure 27: Recommended Circuit for Configuration Pins RM500Q-GL_Hardware_Design 55 / 85...

  • Page 57: Rf Characteristic

    5G Module Series RM500Q-GL Hardware Design RF Characteristic This chapter mainly describes RF characteristics of RM500Q-GL. The module provides four antenna interfaces, ANT0, ANT1, ANT2_GNSSL1 and ANT3 and the impedance of them is 50 Ω. 5.1. Cellular Antenna Interfaces 5.1.1. Pin Definition The pin definition of antenna interfaces is shown below.

  • Page 58: Pin Mapping

    5G Module Series RM500Q-GL Hardware Design 5.1.2. Pin Mapping Table 31: RM500Q-GL Cellular Antenna Mapping 5G NR n77/n78 Antenna WCDMA/LTE (MHz) (MHz) (MHz) (MHz) Refarmed n77/n78/n79 LTE LMHB TRX; ANT0 LMHB TRX TRX1 TRX1 LTE UHB PRX MIMO 617–960 1452–2690 3300–4200 4400–5000 WCDMA LMHB TRX;...
  • Page 59 5G Module Series RM500Q-GL Hardware Design – EGSM (950) 880–915 925–960 – – – – J1700 1750–1785 1845–1880 – – 700 lower A–C 699–716 729–746 – – – 700 upper C 777–787 746–756 – – – 700 D 788–798 758–768 –...

  • Page 60: Receiving Sensitivity

    5G Module Series RM500Q-GL Hardware Design – – – 4400–5000 4400–5000 5.1.4. Receiving Sensitivity The following tables show conducted RF receiving sensitivity of the module. Table 33: RM500Q-GL Conducted RF Receiving Sensitivity Mode Frequency Primary Diversity SIMO 3GPP (SIMO) WCDMA B1 -110 -110.8 -113...
  • Page 61 5G Module Series RM500Q-GL Hardware Design LTE-FDD B19 (10 MHz) -100.3 -100.8 -103.3 -96.3 dBm LTE-FDD B20 (10 MHz) -101 -101.3 -104 -93.3 dBm LTE-FDD B25 (10 MHz) -98.6 -101.2 -92.8 dBm LTE-FDD B26 (10 MHz) -100.6 -101.3 -103.4 -93.8 dBm LTE-FDD B28 (10 MHz) -100.8 -101...

  • Page 62: Output Power

    5G Module Series RM500Q-GL Hardware Design 5G NR-FDD n20 (20 MHz) -92.5 -94.5 -95.5 -89.8 dBm (SCS: 15 kHz) 5G NR-FDD n25 (20 MHz) -90.5 dBm (SCS: 15 kHz) 5G NR-FDD n28 (20 MHz) -99.5 -90.8 dBm (SCS: 15 kHz) 5G NR-TDD n38 (20 MHz) -93.5 -90.6 dBm...

  • Page 63: Gnss Antenna Interface

    5G Module Series RM500Q-GL Hardware Design LTE HPUE bands 26 dBm ± 2 dB (Class 2) < -40 dBm (B38/B40/B41/B42/B43) < -40 dBm 5G NR bands 23 dBm ± 2 dB (Class 3) (BW: 5–20 MHz) 5G NR 5G NR HPUE bands <...

  • Page 64: Gnss Performance

    5G Module Series RM500Q-GL Hardware Design NOTES to 50 Ω. Keep the characteristic impedance for the trace of GNSS antenna (ANT2_GNSSL1) π-type Place the matching components as close to the antenna as possible. Keep the digital circuits, such as that of (U)SIM card, USB interface, camera module, display connector and SD card, away from the antenna traces.

  • Page 65: Antenna Connectors

    5G Module Series RM500Q-GL Hardware Design locked within 3 minutes after the loss of lock. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 5.3. Antenna Connectors 5.3.1.

  • Page 66: Antenna Connector Installation

    5G Module Series RM500Q-GL Hardware Design The connector dimensions are illustrated by the figure below: Figure 29: RM500Q-GL RF Connector Dimensions (Unit: mm) Table 37: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz 50 Ω...
  • Page 67 5G Module Series RM500Q-GL Hardware Design The following figure shows the specifications of mating plugs using Ø 0.81 mm coaxial cables. Figure 30: Specifications of Mating Plugs Using Ø 0.81 mm Coaxial Cables The following figure illustrates the connection between the receptacle RF connector on RM500Q-GL and the mating plug using a Ø...

  • Page 68: Recommended Rf Connector For Installation

    5G Module Series RM500Q-GL Hardware Design The following figure illustrates the connection between the receptacle RF connector on RM500Q-GL and the mating plug using a Ø 1.13 mm coaxial cable. Figure 32: Connection between RF Connector and Mating Plug Using Ø 1.13 mm Coaxial Cable 5.3.4.

  • Page 69: Assemble Coaxial Cable Plug With Jig

    5G Module Series RM500Q-GL Hardware Design The illustration of pulling out the coaxial cable plug is shown below, θ = 90° is acceptable, while θ ≠ 90° is not. Figure 34：Pull out a Coaxial Cable Plug 5.3.4.2. Assemble Coaxial Cable Plug with Jig The pictures of installing the coaxial cable plug with a jig is shown below, θ...

  • Page 70: Recommended Manufacturers Of Rf Connector And Cable

    5G Module Series RM500Q-GL Hardware Design 5.3.5. Recommended Manufacturers of RF Connector and Cable RF connecters and cables by I-PEX are recommended. For more details, visit https://www.i-pex.com. 5.4. Antenna Requirements The following table shows the requirements on WCDMA, LTE, 5G NR antenna and GNSS antenna. Table 38: Antenna Requirements Type Requirements...

  • Page 71: Electrical Characteristics And Reliability

    5G Module Series RM500Q-GL Hardware Design Electrical Characteristics and Reliability 6.1. Power Supply Requirements The typical input voltage of RM500Q-GL is 3.7 V. The following table shows the power supply requirements of RM500Q-GL. Table 39: Power Supply Requirement Parameter Description Min.
  • Page 72 5G Module Series RM500Q-GL Hardware Design LTE-TDD PF = 64 (USB disconnected) 7.04 WCDMA PF = 64 (USB disconnected) 40.97 WCDMA PF = 64 (USB connected) 66.96 LTE-FDD PF = 64 (USB disconnected) 42.56 Idle state LTE-FDD PF = 64 (USB connected) 68.67 LTE-TDD PF = 64 (USB disconnected) 42.67...
  • Page 73 5G Module Series RM500Q-GL Hardware Design LTE-FDD B5 CH20525 @ 23 dBm LTE-FDD B7 CH21100 @ 23 dBm LTE-FDD B8 CH21625 @ 23 dBm LTE-FDD B12 CH23095 @ 23 dBm LTE-FDD B13 CH23230 @ 23 dBm LTE-FDD B14 CH23330 @ 23 dBm LTE-FDD B17 CH5790 @ 23 dBm LTE-FDD B18 CH23925 @ 23 dBm LTE-FDD B19 CH24075 @ 23 dBm...
  • Page 74 5G Module Series RM500Q-GL Hardware Design 5G NR-TDD n41 CH518598 @ 23 dBm 5G NR-TDD n41 CH535998 @ 23 dBm 5G NR-TDD n77 CH620668 @ 23 dBm 5G NR-TDD n77 CH650000 @ 23 dBm 5G NR-TDD n77 CH679332 @ 23 dBm 5G NR-TDD n78 CH620668 @ 23 dBm 5G NR-TDD n78 CH636666 @ 23 dBm 5G NR-TDD n78 CH652666 @ 23 dBm...
  • Page 75 5G Module Series RM500Q-GL Hardware Design 5G NR-FDD n7 CH537000 @ 23 dBm 5G NR-FDD n8 CH186000 @ 23 dBm 5G NR-FDD n8 CH188500 @ 23 dBm 5G NR-FDD n8 CH191000 @ 23 dBm 5G NR-FDD n12 CH146800 @ 23 dBm 5G NR-FDD n12 CH147500 @ 23 dBm 5G NR-FDD n12 CH148200 @ 23 dBm 5G NR-FDD n20 CH159200 @ 23 dBm...

  • Page 76: Digital I/O Characteristic

    5G Module Series RM500Q-GL Hardware Design WCDMA B1 CH10700 @ 23 dBm WCDMA B2 CH9800 @ 23 dBm WCDMA B3 CH1338 @ 23 dBm WCDMA B4 CH1638 @ 23 dBm WCDMA B5 CH4408 @ 23 dBm WCDMA voice call WCDMA B6 CH4175 @ 23 dBm WCDMA B8 CH3012 @ 23 dBm WCDMA B19 CH338 @ 23 dBm 6.3.

  • Page 77: Electrostatic Discharge

    5G Module Series RM500Q-GL Hardware Design Table 43: (U)SIM 3.0V I/O Requirements Parameter Description Min. Max. Unit USIM_VDD Power supply 3.05 Input high voltage 0.7 × USIM_VDD USIM_VDD + 0.3 Input low voltage -0.3 0.2 × USIM_VDD Output high voltage 0.8 ×...
  • Page 78 5G Module Series RM500Q-GL Hardware Design Figure 36: Thermal Dissipation Area Inside and on Bottom Side of the Module (Unit: mm) There are other measures to enhance heat dissipation performance: ⚫ Add as many ground vias as possible on the PCB. ⚫...

  • Page 79: Absolute Maximum Ratings

    5G Module Series RM500Q-GL Hardware Design 6.6. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 45: Absolute Maximum Ratings Parameter Min. Typ. Max.

  • Page 80: Mechanical Dimensions And Packaging

    5G Module Series RM500Q-GL Hardware Design Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM500Q-GL module. All dimensions are measured in mm, and the tolerances are ± 0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 37: Mechanical Dimensions of RM500Q-GL (Unit: mm) RM500Q-GL_Hardware_Design 79 / 85...

  • Page 81: Top And Bottom Views Of The Module

    NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. 7.3. M.2 Connector RM500Q-GL adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in PCI Express M.2 Specification Revision 3.0, Version 1.2.

  • Page 82: Packaging

    5G Module Series RM500Q-GL Hardware Design 7.4. Packaging RM500Q-GL modules are packaged in trays. The following figure shows the tray size. Figure 39: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below.

  • Page 83: Appendix References

    5G Module Series RM500Q-GL Hardware Design Appendix References Table 47: Related Documents Document Name Description Quectel_RM500Q_Series_Reference_Design RM500Q-GL reference design CA&ENDC combinations of Quectel_RM50xQ-GL_CA&EN-DC_Features RM500Q-GL Quectel_PCIe_Card_EVB_User_Guide PCIe card EVB user guide Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_ AT commands manual for RG50xQ Manual series and RM5xxQ series RM500Q+IPQ8074A reference Quectel_RM500Q_Series+IPQ8074A_Reference Design design...
  • Page 84 5G Module Series RM500Q-GL Hardware Design DFOTA Delta Firmware Upgrade Over-The-Air Downlink Dynamic Power Reduction Discontinuous Reception (Chapter 3.1.1) Diversity Reception (Chapter 5) EIRP Equivalent Isotropically Radiated Power Electromagnetic Interference Electrostatic Discharge Frequency Division Duplexing GLONASS Global Navigation Satellite System (Russia) GNSS Global Navigation Satellite System Global Positioning System...
  • Page 85 5G Module Series RM500Q-GL Hardware Design MLCC Multilayer Ceramic Chip Capacitor Mobile Originated Most Signification Bit Mobile Terminated Password Authentication Protocol Printed Circuit Board PCIe Peripheral Component Interconnect Express Pulse Code Modulation Protocol Data Unit Point-to-Point Protocol Qualcomm MSM (Mobile Station Modems) Interface Root Complex Radio Frequency RFFE...
  • Page 86 5G Module Series RM500Q-GL Hardware Design Unsolicited Result Code Universal Serial Bus (U)SIM (Universal) Subscriber Identity Module Input High Voltage Level Input Low Voltage Level Output High Voltage Level Output Low Voltage Level VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network RM500Q-GL_Hardware_Design...

This manual is also suitable for:

Rm500q-gl

Table of Contents