Quectel RG520N-AT Hardware Design page 30

Table of Contents

Advertisement

Other Interface Pins
Pin Name
USB_BOOT
EXT_RST
EXT_INT
W_DISABLE#
ETH1_PWR_EN
ETH2_PWR_EN
ETH1_INT_N
ETH2_INT_N
RESERVED Pins
Pin Name
RESERVED
NOTE
RG520N-AT has 5 antenna interfaces (ANT0/ANT1/ANT2/ANT3 + ANT_GNSS).
RG520N-AT_Hardware_Design
synchronization
Pin No.
I/O
Description
Forces the module
81
DI
into emergency
download mode
External audio
75
DO
reset
External audio
281
DI
interrupt
Airplane mode
114
DI
control
Ethernet
220
DO
power enable
Ethernet
223
DO
power enable
Interrupts input
221
DI
from
1
Interrupts input
104
DI
from
2
Pin No.
1–6, 9, 10, 11, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25,
27, 28, 29, 31, 45, 54, 57, 58, 69, 72, 80, 87, 92–95, 97, 99,
101, 103, 106, 111, 117, 120, 139, 148, 150, 153, 165, 177,
183, 186, 189, 192, 198, 199, 208, 217, 218, 239, 242, 260,
262–265, 270, 271–273, 274, 277–280, 282–298
DC
Characteristics
1.8 V
PHY 1
PHY 2
Ethernet
PHY
Ethernet
PHY
5G Module Series
Support.
Comment
A test point is
recommended to be
reserved.
These pins are the
control pins of PHY
chip recommended
by the platform.
Comment
Keep these pins
unconnected.
29 / 109

Advertisement

Table of Contents
loading

Table of Contents