I2S Interface - Quectel RG520N-AT Hardware Design

Table 16: Pin Definition of I2C Interface
Pin Name
I2C_SCL
I2C_SDA
4.5. I2S Interface*
The module provides one I2S interface.
Pin definition is listed as follows:
Table 17: Pin Definition of I2S Interface
Pin Name
I2S_WS
I2S_SCK
I2S_DIN
I2S_DOUT
MCLK
The following figure shows a reference design of I2S interface with an external codec IC.
RG520N-AT_Hardware_Design
Pin No. I/O
77 OD
78 OD
Pin No. I/O
259 DIO
256 DIO
257 DI
255 DO
79 DO
Description
I2C serial clock
I2C serial data
Description
I2S word select
I2S clock
I2S data in
I2S data out
Master clock output for
codec
5G Module Series
Comment
Pull them up to VDD_EXT
with an external 4.7 kΩ
resistor respectively. If
unused, keep them open.
Comment
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
If unused, keep it open.
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