Quectel RG520N-AT Hardware Design page 54

The module supports 16-bit linear data format. The following figures show the primary mode's timing
relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary mode's timing
relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK.
P CM _CLK
P CM _S YNC
P CM _DOUT
P CM _DIN
P CM _CLK
P CM _S YNC
P CM _DOUT
P CM _DIN
Clock and mode can be configured via AT+QDAI, and the default configuration is master mode using
short frame sync format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [3] about
AT+QDAI for details.
RG520N-AT_Hardware_Design
125 μs
1 2
MS B LS B
MS B
Figure 23: Primary Mode Timing
125 μs
1 2
MS B
MS B
Figure 24: Auxiliary Mode Timing
2 5 5 2 5 6
MS B
MS B
LS B
31 32
LS B
LS B
5G Module Series
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