Quectel RG520N-AT Hardware Design page 29

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ANT3
ANT_GNSS
Antenna Tuner Control
Pin Name
SDR_GRFC0
SDR_GRFC1
SPI
Pin Name
SPI_CLK
SPI_CS
SPI_MISO
SPI_MOSI
ADC Interface
Pin Name
ADC0
Time Service and Repeater Interface
Pin Name
GPIO_32
RG520N-AT_Hardware_Design
-
Antenna 3 interface:
-
184
AIO
-
-
GNSS antenna interface:
193
AI
-
Interfaces*
Pin No.
I/O
Description
GRFC interfaces
171
DO
dedicated for
external antenna
174
DO
tuner control
Pin No.
I/O
Description
210
DO
SPI clock
207
DO
SPI chip select
SPI master-in
213
DI
slave-out
SPI master-out
204
DO
slave-in
Pin No.
I/O
Description
General-purpose
241
AI
ADC interface
Pin No.
I/O
Description
Supports time
service and
repeater functions;
98
DO
supports 1PPS
pulse output and
frame
Refarmed: LMB_DRX MIMO &
HB_PRX MIMO
5G NR: n77 TRX1
LTE: LMB_TRX1 & HB_TRX0
Refarmed: LMB_TRX1 &
HB_TRX0
L1/L5
DC
Characteristics
1.8 V
DC
Characteristics
1.8 V
DC
Characteristics
Voltage range:
0–1.875 V
DC
Characteristics
1.8 V
5G Module Series
Comment
If unused, keep
them open.
Comment
Only master mode is
supported.
Comment
Comment
The pin can be
multiplexed into
AP2SDX_STATUS
function.
For details, contact
Quectel Technical
28 / 109

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