Functional Diagram - Quectel RG520N-AT Hardware Design

2.3. Functional Diagram

The following figure shows a block diagram of the module and illustrates the major functional parts.
⚫
Power management
⚫
Baseband
⚫
DDR + NAND flash
⚫
Radio frequency
⚫
Peripheral interfaces
VBAT_RF
VDD_WIFI_VL
VDD_WIFI_VM
VDD_WIFI_VH
VBAT_BB
PMIC
PWRKEY
RESET_N
ADC
STATUS
VDD_EXT
RG520N-AT_Hardware_Design
QET
RFCLK
76.8 MHz
QLINK
BBCLK(19.2 MHz)
SleepCLK(32.768 kHz)
PMU
76.8 MHz
XO
SPMI
eSIM
(U)SIM2 (U)SIM1
Figure 1: Functional Diagram
Tx/Rx Blocks
Transceiver
Control
Baseband
PCIe
USB_BOOT
PCM SPI
USB
3.0
2.0/3.1
5G Module Series
NAND
LPDDR4X
SDRAM
W_DISABLE＃
Indication Signals
I2C UART SDIO
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