Quectel RG520N-AT Hardware Design page 27

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BT_EN
WLAN_EN
WL_SW_CTRL
WLAN_SLP_CLK
RF_CLK3_WL
SDX_TO_WL_
CTI
WLAN_PA_
MUTING
WL_LAA_AS_EN
WL_LAA_RX
WL_TO_SDX_
CTI
SDIO Interface
Pin Name
RG520N-AT_Hardware_Design
Bluetooth enable
64
DO
control
WLAN function
222
DO
enable control
76.8 MHz system
180
DI
clock request
32.768 kHz sleep
225
AO
clock output
76.8 MHz system
246
AO
clock output
276
DO
-
GPIO from SDX to
162
DO
disable WLAN PA
GPIO allows SDR
to power on
monitoring for
WCN when WLAN
is sleeping or
disabled.
159
DO
Additionally, the
control logic in
WLAN AON
domain allows
SDR to control 5G
WLAN xLNA (LNA
in FEMs).
SoC signal to set
5G xLNA to high
gains or high
isolation when
both chains (LAA
201
DO
and 5G WLAN)
are active
simultaneously. No
individual control
for each chain.
275
DI
-
Pin No.
I/O
Description
5G Module Series
Vmax = 1.08 V
Vnom = 1.05 V
Vmin = 1.02 V
Not used by default.
Keep it open.
1.8 V
Not used by default.
Keep it open.
DC
Comment
26 / 109

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