To Configure Data Memory Write Operations (Powerpc 400, 603E, 603Ev, 603E2, 603P, 603Ec, 603R, 740, 750, 750M, 740P, 750P); Data Memory Write Operation - Agilent Technologies E5900B User Manual

Chapter 7: Configuring the Emulation Probe
Configuration items
To configure data memory write operations
(PowerPC 400, 603e, 603ev, 603e2, 603P, 603ec, 603R,
740, 750, 750M, 740P, 750P)
Although the PowerPC processor has one contiguous physical memory
address space that can hold both data and instructions, it has separate caches
for instructions and data. These separate caches must be considered in order
to keep the caches and memory coherent during memory write operations.
These settings are only used for data memory write operations. Code
download always writes to physical memory and disables any cache entries
containing addresses written for improved performance. Some host interfaces
use the code download mode for all memory write operations so this setting
may or may not have any effect on your debugger.
Only the memory write command allows specifying instruction or data
memory operations. This may not be provided by your debugger interface. If
not specified, memory write operations are always instruction memory.
If the data cache is disabled, a data memory write will always write to physical
memory and this configuration setting is ignored.
Data memory write configuration
Command
cf dmwrop=mm
cf dmwrop=thru
cf dmwrop=bypass
The cf dmwrop=bypass setting should be used with extreme caution because
dirty cache entries may be written by the processor over the new data value
88 Agilent Technologies Emulation for the PowerPC 400/600/700
emulation probe configured for
Data writes to addresses that are valid in the data cache
will write the value only to the cache and mark the cache
line modified as "dirty", which will indicate to the CPU that
the cache line must be written to memory. A data write
that is not valid in the data cache will only be written to
physical memory. (Default)
A data memory write to an address that is valid in the
data cache will write to both cache and physical memory.
If the address is not valid in the cache, only physical
memory will be modified.
A data memory write will only be written to physical
memory, ignoring the cache.