To Enable Or Disable Processor Caches - Agilent Technologies E5900B User Manual

Chapter 7: Configuring the Emulation Probe
Configuration items

To enable or disable processor caches

The PowerPC 7XX processors have instruction and data caches. Debugging
using a third party debugger will have the greatest performance if the caches
are disabled during debugging. There are three ways to disable the caches
prior to a debug session:
• Clear bits HID0[ICE] and HID0[DCE]. This will turn off the instruction
and data caches. Also turn off the L2 Cache, by setting L2CR to zero.
Ensure that your startup code does not reset the HID0 or L2CR registers
because this could re-enable the caches.
• (PowerPC 740/750 Only) Issue the following probe commands:
"cf reset=rom"
"rst" ("rst" will turn off all caches)
Ensure that your startup code does not reset the HID0 register after the "rst"
command because this could re-enable the caches.
• (PowerPC 740/750 Only) Keep the caches enabled but tell the
emulation probe to bypass them. To do this, issue the probe
commands:
"cf mrdop=phys" (so only physical memory is read)
"cf dmwrop=bypass" (to bypass the updating of the data cache)
all addresses with the @dmem modifier.
Example
M> cf mrdop=phys
M> cf dmwrop=bypass
M> m -d4 -a4 0..
M> m -d4 -a4 0@dmem=12345678 (this will write physical memory only)
When caches are bypassed, all memory accesses occur out of physical
memory and the cache information is ignored. This means that cache
coherency is not maintained.
If cache handling is not modified using one of the above three methods, execution
with the third party debugger may be slower due to the emulation probe making
sure the cache information stays coherent with physical memory.
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(this will read physical memory only)
Agilent Technologies Emulation for the PowerPC 400/600/700
reference