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CAUTION:
To configure the memory read operation
(PowerPC 400, 603e, 603ev, 603e2, 603P, 603ec, 603R,
740, 750, 750M, 740P, 750P)
Although PowerPC processors have one contiguous physical address space
that can hold both data and instructions, it is necessary to differentiate
between data spaces and instruction spaces when dealing with a memory/
cache coherency model during a write memory operation.
The memory read operation configuration entry defines how the memory and
cache interact during a memory read operation. If both instruction and data
caches are turned off (bits ICE and DCE in the register HID0 are zero), this
configuration setting has no effect and a memory read will always return the
contents of physical memory.
Memory read configuration
Command
cf mrdop=mm
cf mrdop=phys
Using the mrdop=phys setting with the cache enabled may show data that is
no longer valid. Use this setting only for solving cache problems where you
really need to see the contents of physical memory. For general operation, the
"mm" setting should always be used.
The instruction cache in PPC740 and PPC750 is encoded. The emulation
probe will decode the content of the instruction cache before displaying it.
However, the emulation probe will only decode valid instructions. Invalid
instructions in the cache will be displayed in coded form, which might not
match the content of memory.
Agilent Technologies Emulation for the PowerPC 400/600/700
Chapter 7: Configuring the Emulation Probe
emulation probe configured for
A memory read from an address that is valid in either the
data or instruction cache will return the contents of the
cache. Memory reads from addresses not valid in either
cache will return the contents of the physical memory.
(Default)
A memory read will always return the contents of
physical memory.
Configuration items
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