To Enable Or Disable Processor Caches - Agilent Technologies E5900B User Manual

Chapter 7: Configuring the Emulation Probe

To enable or disable processor caches

To enable or disable processor caches
PowerPC 6XX and 7XX processors have instruction and data caches.
Debugging using a third party debugger will have the greatest performance if
the caches are disabled during debugging.
To turn off the caches clear bits HID0[ICE] and HID0[DCE]. This will turn off
the instruction and data caches. You may need to ensure that your start up
code does not enable the caches.
You may also debug with the caches enabled. To achieve maximum
performance you should disable and invalidate the caches while downloading
a program. You can do this by setting bits HID0[ICFI] and HID0[DCFI]. After
downloading a program you may want to enable the caches by setting bits
HID0[ICE] and HID0[DCE].
Performance will be slower when debugging with the caches enabled due to
the emulation probe making sure the cache information stays coherent with
the physical memory.
In addition, PowerPC 750/755 processors have L2 cache. Set L2CR=0 to
disable the L2 cache to achieve the fastest performance when debugging.
To invalidate the L2 cache, set L2CR[L2I]. Refer to the processor user's guide
for instructions on enabling the L2 cache.
PowerPC 4XX processors have instruction and data caches. Refer to the
processor user's guide for instructions on enabling and disabling caches. The
debugger software will run fastest when caches are disabled.
Agilent Technologies Emulation for the PowerPC 400/600/700 103