To Set The Memory Read Delay Clock Cycles (Powerpc 603Ei, 745, 755); Memory Read Delay - Agilent Technologies E5900B User Manual

To set the memory read delay clock cycles
(PowerPC 603ei, 745, 755)
The memory read delay is provided for accessing slow devices like memory
mapped I/O.
The memory read delay delays all memory reads the amount of time
calculated using parameters entered by the user. The user specifies the core
clock frequency. The user adjusts the delay with the number of clock cycles
entered.
The number of clock cycles should be set to the smallest number possible for
best performance since it delays all memory reads by the amount of time
calculated.
Memory Read Delay Clock Cycles
Command
cf mrddelcyc= <clock cycles> @ <core clock speed>
Example: cf mrddelcyc=300@400
This delays all reads 750 ns (300 cycles at 400 MHz).
Values
0-4 000 000 000 clock cycles @ 100-700 MHz core clock speed.
(Default = no delay)
Agilent Technologies Emulation for the PowerPC 400/600/700
Chapter 7: Configuring the Emulation Probe
Configuration items
91