To Enable Or Disable Data Parity (Powerpc 603E, 603Ev, 603E2, 603P, 603Ec, 603R, 740, 750, 750M, 740P, 750P) - Agilent Technologies E5900B User Manual

To enable or disable data parity
(PowerPC 603e, 603ev, 603e2, 603P, 603ec, 603R, 740,
750, 750M, 740P, 750P)
The PowerPC processor generates parity bits on both address and data lines
when running user code. When used in debug mode these bits must be
generated separately, which slows down memory operations. Since memory
operations on the PowerPC are already slow and many target systems do not
check parity, the default for this configuration item is "off."
Parity configuration
Command
cf parity=off
cf parity=on
Agilent Technologies Emulation for the PowerPC 400/600/700
Chapter 7: Configuring the Emulation Probe
Emulation probe configured for
Do not generate the parity bits for memory operations
from the emulation probe. This provides better
performance, but will not work correctly when accessing
devices that check the parity bits. (Default)
Generate the parity bits for memory operations. Currently,
only parity bits for the memory data lines are generated.
Parity bits on the address lines are not. This may change
in future firmware versions.
Configuration items
101