Interfacing To A Microcontroller/Dsp - Analog Devices ADF7021-V Manual

ADF7021-V
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers. The silicon revision word is coded with four
quartets in BCD format. The product code (PC) is coded with
three quartets extending from Bit RV16 to Bit RV5. The revision
code (RC) is coded with one quartet extending from Bit RV4 to
Bit RV1. The product code for the ADF7021-V should read back as
PC = 0x212. The current revision code should read as RC = 0x0.
Filter Bandwidth Calibration Readback
The filter calibration readback word is contained in Bit RV8 to
Bit RV1 (see Figure 57). This readback can be used for manual
filter adjustment, thereby avoiding the need to do an IF filter
calibration in some instances. The manual adjust value is
programmed using Register 5, Bits[DB19:DB14]. To calculate
the manual adjustment based on a filter calibration readback,
use the following formula:
IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128
The result should be programmed into Register 5, Bits[DB19:DB14]
as described in the Register 5—IF Filter Setup Register section.

INTERFACING TO A MICROCONTROLLER/DSP

Standard Transmit/Receive Data Interface
The standard transmit/receive signal and configuration interface
to a microcontroller is shown in Figure 58. In transmit mode, the
ADF7021-V provides the data clock on the TxRxCLK pin, and
the TxRxDATA pin is used as the data input. The transmit data
is clocked into the ADF7021-V on the rising edge of TxRxCLK.
ADuC84x
MISO
MOSI
SCLOCK
SS
P3.7
P3.2/INT0
P2.4
P2.5
GPIO
P2.6
P2.7
Figure 58. ADuC84x to ADF7021-V Connection Diagram
In receive mode, the ADF7021-V provides the synchronized
data clock on the TxRxCLK pin. The received data is available
on the TxRxDATA pin. The rising edge of TxRxCLK should be
used to clock the receive data into the microcontroller. See
Figure 4 and Figure 5 for the relevant timing diagrams.
In 4FSK transmit mode, the MSB of the transmit symbol is
clocked into the ADF7021-V on the first rising edge of the data
clock from the TxRxCLK pin. In 4FSK receive mode, the MSB
of the first payload symbol is clocked out on the first falling edge
of the data clock after the SWD and should be clocked into the
microcontroller on the following rising edge. See Figure 6 and
Figure 7 for the relevant timing diagrams.
ADF7021-V
TxRxDATA
TxRxCLK
CE
SWD
SREAD
SLE
SDATA
SCLK
Rev. 0 | Page 44 of 60
UART Mode
In UART mode, the TxRxCLK pin is configured to input trans-
mit data in transmit mode. In receive mode, the receive data is
available on the TxRxDATA pin, thus providing an asynchronous
data interface. The UART mode can only be used with oversampled
2FSK modulation. Figure 59 shows a possible interface to a micro-
controller using the UART mode of the ADF7021-V. To enable the
UART interface mode, set Bit DB28 in Register 0 high. Figure 8
and Figure 9 show the relevant timing diagrams for UART mode.
MICROCONTROLLER
TxDATA
UART
RxDATA
GPIO
Figure 59. ADF7021-V (UART Mode) to Asynchronous Microcontroller Interface
SPI Mode
In SPI mode, the TxRxCLK pin is configured to input transmit
data in transmit mode. In receive mode, the receive data is avail-
able on the TxRxDATA pin. The data clock in both transmit and
receive modes is available on the CLKOUT pin. In transmit mode,
data is clocked into the ADF7021-V on the rising edge of
CLKOUT. In receive mode, the TxRxDATA data pin should be
sampled by the microcontroller on the rising edge of CLKOUT.
To enable SPI interface mode, set Bit DB28 in Register 0 high
and set Bits[DB19:DB17] in Register 15 to 0x7. Figure 8 and
Figure 9 show the relevant timing diagrams for SPI mode;
Figure 60 shows the recommended interface to a micro-
controller using the SPI mode of the ADF7021-V.
MICROCONTROLLER
MISO
MOSI
SPI
SCLK
GPIO
Figure 60. ADF7021-V (SPI Mode) to Microcontroller Interface
ADSP-BF533 Interface
The suggested method of interfacing to the Blackfin®
ADSP-BF533 is shown in Figure 61.
ADSP-BF533
SCK
MOSI
MISO
PF5
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
Figure 61. ADSP-BF533 to ADF7021-V Connection Diagram
ADF7021-V
TxRxCLK
TxRxDATA
CE
SWD
SREAD
SLE
SDATA
SCLK
ADF7021-V
TxRxCLK
TxRxDATA
CLKOUT
CE
SWD
SREAD
SLE
SDATA
SCLK
ADF7021-V
SCLK
SDATA
SREAD
SLE
TxRxCLK
TxRxDATA
SWD
CE