Digital Specifications - Analog Devices ADF7021-V Manual

DIGITAL SPECIFICATIONS

Table 4.
Parameter
TIMING INFORMATION
Chip Enabled to Regulator
Ready
Chip Enabled to Tx Mode
TCXO Reference
XTAL
Chip Enabled to Rx Mode
TCXO Reference
XTAL
Tx-to-Rx Turnaround Time
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I /I
INH INL
Input Capacitance, C
IN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
CLKOUT Rise/Fall Time
CLKOUT Load
Min Typ
50
1
2
1.2
2.2
AGC settling +
(5 × t )
BIT
0.7 × V
DD
VDD2 − 0.4
Rev. 0 | Page 9 of 60
Max Unit Test Conditions/Comments
μs CREG[1:4] = 100 nF
32-bit register write time = 50 μs
ms Depends on VCO settling
ms Depends on VCO settling
32-bit register write time = 50 μs, IF filter coarse
calibration only
ms Depends on VCO settling
ms Depends on VCO settling
ms Time to synchronized data output; includes AGC
settling (three AGC levels) and CDR synchronization;
t = data bit period; AFC settling not included
BIT
V
0.2 × V V
DD
±1 μA
10 pF
50 MHz
V I = 500 μA
OH
0.4 V I = 500 μA
OL
5 ns
10 pF
ADF7021-V