Analog Devices ADF7021-V Manual page 25

Setting the Transmit Data Rate
In all modulation modes except for oversampled 2FSK mode, an
accurate clock is provided on the TxRxCLK pin to latch the data
from the microcontroller into the transmit section at the required
data rate. The exact frequency of this clock is defined by
=
DATA CLK
DEMOD_CLK_
where:
XTAL is the crystal or TCXO frequency.
DEMOD_CLK_DIVIDE is the divider that sets the demodulator
clock rate (Register 3, Bits[DB9:DB6]).
CDR_CLK_DIVIDE is the divider that sets the CDR clock rate
(Register 3, Bits[DB17:DB10]).
See the Register 3—Transmit/Receive Clock Register section for
more programming information.
Setting the FSK Transmit Deviation Frequency
In all modulation modes, the deviation from the center
frequency is set using the Tx_FREQUENCY_DEVIATION
bits (Register 2, Bits[DB27:DB19]).
The deviation from the center frequency in Hz is as follows:
For direct RF output,
×
PFD Tx_FREQUEN
=
f (Hz)
DEV
With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled,
PFD
= ×
f (Hz) 0 5 .
DEV
where Tx_FREQUENCY_DEVIATION is a number from 1 to
511 (Register 2, Bits[DB27:DB19]).
In 4FSK modulation, the four symbols (00, 01, 11, 10) are
transmitted as ±3 × f and ±1 × f
DEV
Binary Frequency Shift Keying (2FSK)
Binary frequency shift keying is implemented by setting the
N value for the center frequency and then toggling it with the
TxRxDATA line. The deviation from the center frequency is set
using the Tx_FREQUENCY_DEVIATION bits (Register 2,
Bits[DB27:DB19]).
2FSK is selected by setting the MODULATION_SCHEME bits
(Register 2, Bits[DB6:DB4]) to 000.
Minimum shift keying (MSK) or Gaussian minimum shift
keying (GMSK) is supported by selecting 2FSK modulation
and using a modulation index of 0.5. A modulation index of 0.5
is set by configuring Register 2, Bits[DB27:DB19] for an
= 0.25 × transmit data rate.
f
DEV
XTAL
×
DIVIDE CDR_CLK_DI VIDE
CY_DEVIATI ON
16
2
×
Tx_FREQUEN CY_DEVIATI
16
2
.
DEV
Three-Level Frequency Shift Keying (3FSK)
In three-level FSK modulation—3FSK, also known as modified
duobinary FSK and as partial response maximum likelihood
Class 4 (PRML4) signaling—the binary data (Logic 0 and Logic 1)
is mapped onto three distinct frequencies: the carrier frequency
(f ), the carrier frequency minus a deviation frequency (f
C
and the carrier frequency plus the deviation frequency (f
×
32
A Logic 0 is mapped to the carrier frequency, whereas a Logic 1
is mapped onto either the f
frequency.
Figure 41. 3FSK Symbol-to-Frequency Mapping
Compared with 2FSK, this bit-to-frequency mapping results
in a reduced transmission bandwidth because some energy is
removed from the RF sidebands and transferred to the carrier
frequency. At low modulation index, 3FSK improves the trans-
mit spectral efficiency by up to 25% when compared with 2FSK.
The bit-to-symbol mapping for 3FSK is implemented using a
linear convolutional encoder that also permits Viterbi detection
to be used in the receiver. A block diagram of the transmit hard-
ware used to realize this system is shown in Figure 42. The
convolutional encoder polynomial used to implement the
ON
transmit spectral shaping is
P(D) = 1 − D
where:
P is the convolutional encoder polynomial.
D is the unit delay operator.
A digital precoder with transfer function 1/P(D) implements
an inverse modulo-2 operation of the 1 − D
the transmitter.
Tx DATA
0, 1
PRECODER
1/P(D)
Rev. 0 | Page 25 of 60
− f frequency or the f
C DEV
0
+1
–1
f f f f f
– +
C DEV C C DEV
RF FREQUENCY
2
2
shaping filter in
0, 1
CONVOLUTIONAL
ENCODER
P(D)
0, +1, –1
f
C
f f
FSK MOD +
C
f f
CONTROL –
C
AND
DATA FILTERING
Figure 42. 3FSK Encoding
ADF7021-V
− f ),
C DEV
+ f ).
C DEV
+ f
C DEV
DEV
DEV
TO
N DIVIDER