Analog Devices ADF7021-V Manual page 16

ADF7021-V
Pin No. Mnemonic
27 SREAD
28 SCLK
29 GND2
30 ADCIN
31 CREG2
32 VDD2
33 SWD
34 TxRxDATA
35 TxRxCLK
36 CLKOUT
37 MUXOUT
38 OSC2
39 OSC1
40 VDD3
41 CREG3
42 CPOUT
43 VDD
44 L2
45 GND
46 L1
47 GND1
48 CVCO
EP Exposed Paddle
Description
Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The
SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched
into the 32-bit shift register on the SCLK rising edge. This pin is a digital CMOS input.
Ground for Digital Block. Tie all GND pins together.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is
0 V to 1.9 V. Readback is through the SREAD pin.
Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator
stability and noise rejection.
Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie
all VDDx pins together.
Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence.
This provides an interrupt for an external microcontroller, indicating that valid data is being received.
Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI
receive mode, this pin provides an output for the received data. In UART/SPI transmit mode, this pin is
high impedance.
Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels
apply. The positive clock edge is matched to the center of the received data. In standard transmit mode,
this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at
the exact required data rate. In UART/SPI transmit mode, this pin is used to input the transmit data. In
UART/SPI receive mode, this pin is high impedance.
Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used
to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark/space
ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the
pin in applications where the CLKOUT feature is used.
Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine whether the PLL is locked to
the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of
the status of the serial interface regulator.
Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this
pin with CMOS levels and disabling the internal crystal oscillator.
Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this
pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator.
Voltage Supply for Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Tie
all VDDx pins together.
Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Voltage Supply for RF Circuitry. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie
all VDDx pins together.
VCO Buffer Input.
Ground. Tie all GND pins together.
Do not connect.
Ground. Tie all GND pins together.
Do not connect.
The exposed paddle must be connected to the ground plane.
Rev. 0 | Page 16 of 60