Receiver Setup - Analog Devices ADF7021-V Manual

ADF7021-V

RECEIVER SETUP

Correlator Demodulator Setup
To enable the correlator for various modulation modes, see
Table 15.
Table 15. Enabling the Correlator Demodulator
Received Modulation
2FSK
3FSK
4FSK
To optimize receiver sensitivity, the correlator bandwidth must
be optimized for the specific deviation frequency and modula-
tion used by the transmitter. The discriminator bandwidth is
controlled by Register 4, Bits[DB19:DB10], and is defined as
DISCRIMINA TOR _ BW
where:
DEMOD CLK is as defined in the Register 3—Transmit/Receive
Clock Register section.
K is set for each modulation mode as follows:
For 2FSK,
⎛
×
3
100 10
⎜
=
K Round
⎜
⎝ f
DEV
For 3FSK,
⎛ ⎞
×
3
100 10
⎜ ⎟
=
K Round
⎜ ⎟
×
⎝ 2 f ⎠
DEV
For 4FSK,
⎛
×
100 10
⎜
=
K Round
⎜
×
4FSK
⎝ 4 f
DEV
where:
Round is rounded to the nearest integer.
Round is rounded to the nearest of the following integers:
4FSK
32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.
f is the transmit frequency deviation in Hz. For 4FSK, f
DEV
is the frequency deviation used for the ±1 symbols (that is, the
inner frequency deviations).
To optimize the coefficients of the correlator, Register 4, Bit DB7
and Register 4, Bits[DB9:DB8] must also be assigned. The value
of these bits depends on whether K is odd or even. These bits
are assigned according to Table 16 and Table 17.
Table 16. Assignment of Correlator K Value for 2FSK and 3FSK
K K/2 (K + 1)/2
Even Even N/A
Even Odd N/A
Odd N/A Even
Odd N/A Odd
DEMOD_SCHEME
(Register 4, Bits[DB6:DB4])
001
010
011
( )
×
DEMOD CLK K
=
×
3
400 10
⎞
⎟
⎟
⎠
⎞
3
⎟
⎟
⎠
Register 4, Register 4,
Bit DB7 Bits[DB9:DB8]
0 00
0 10
1 00
1 10
Table 17. Assignment of Correlator K Value for 4FSK
K
Even
Odd
Linear Demodulator Setup
The linear demodulator can be used for 2FSK demodulation. To
enable the linear demodulator, set the DEMOD_SCHEME bits
(Register 4, Bits[DB6:DB4]) to 000.
Postdemodulator Filter Setup
The 3 dB bandwidth of the postdemodulator filter should be
set according to the received modulation type and data rate.
The bandwidth is controlled by Register 4, Bits[DB29:DB20]
and is given by
POST _
where f
CUTOFF
demodulator filter.
Table 18. Postdemodulator Filter Bandwidth Settings for
2FSK/3FSK/4FSK Modulation Schemes
Received
Modulation
2FSK
3FSK
4FSK
3FSK Viterbi Detector Setup
The Viterbi detector can be used for 3FSK data detection; it is
activated by setting Register 13, Bit DB11, to Logic 1.
The Viterbi path memory length is programmable in steps of
4, 6, 8, or 32 bits (VITERBI_PATH_MEMORY, Register 13,
Bits[DB14:DB13]). The path memory length should be set
equal to or greater than the maximum number of consecutive
0s in the interleaved transmit bit stream.
The Viterbi detector also uses threshold levels to implement the
maximum likelihood detection algorithm. These thresholds are
programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits
(Register 13, Bits[DB10:DB4]).
DEV
These bits are assigned as follows:
3FSK/4FSK_SLICER_THRESHOLD =
⎛
Tx
⎜
×
7 5
⎜
⎝
where K is the value calculated for correlator discriminator
bandwidth.
3FSK Threshold Detector Setup
To activate threshold detection of 3FSK, Register 13, Bit DB11,
should be set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD
bits (Register 13, Bits[DB10:DB4]) should be set as described in
the 3FSK Viterbi Detector Setup section.
Rev. 0 | Page 32 of 60
Register 4, Bit DB7 Register 4, Bits[DB9:DB8]
0 00
1 00
× ×
11
2 π f
=
CUTOFF
DEMOD _ BW
DEMOD
is the target 3 dB bandwidth in Hz of the post-
Postdemodulator Filter Bandwidth,
f (Hz)
CUTOFF
0.75 × data rate
1 × data rate
1.6 × symbol rate (0.8 × data rate)
_ FREQUENCY _ DEVIATION
×
3
100 10
CLK
⎞
×
K
⎟
⎟
⎠