Timing Diagrams - Analog Devices ADF7021-V Manual

TIMING DIAGRAMS

Serial Interface
SCLK
SDATA DB31 (MSB)
SLE
t
1
SCLK
SDATA
REG 7 DB0
(CONTROL BIT C1)
SLE
t
3
SREAD
2FSK/3FSK Timing
TxRxCLK
TxRxDATA
TxRxCLK
TxRxDATA
t t
1 2
DB30
(CONTROL BIT C3)
Figure 2. Serial Interface Timing Diagram
t
2
X RV16
t
t
9
8
Figure 3. Serial Interface Readback Timing Diagram
±1 × DATA RATE/32
DATA
Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode
DATA
FETCH SAMPLE
Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode
Rev. 0 | Page 11 of 60
t t
3 4
DB2 DB1
(CONTROL BIT C2)
RV15
1/DATA RATE
1/DATA RATE
ADF7021-V
DB0 (LSB)
(CONTROL BIT C1)
t
6
t
5
t
10
RV2 RV1 X