Analog Devices ADF7021-V Manual page 29

Offset Correction Clock
In Register 3, the user should set the BBOS_CLK_DIVIDE bits
(Bits[DB5:DB4]) to give a baseband offset clock (BBOS CLK)
frequency between 1 MHz and 2 MHz.
BBOS CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)
where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32.
AGC Information and Timing
AGC is selected by default and operates by setting the appro-
priate LNA and filter gain settings for the measured RSSI level.
To enter one of the LNA/mixer modes listed in Table 14, the
user can disable AGC by writing to Register 9. After each gain
change, the AGC loop waits for a programmed time to allow
transients to settle. This AGC update rate is set according to
AGC Update Rate (Hz) =
where:
SEQ_CLK_DIVIDE = 100 kHz (Register 3, Bits[DB25:DB18]).
AGC_CLK_DIVIDE is set by Register 3, Bits[DB31:DB26]. A
value of 33 is recommended.
It is recommended that AGC_CLK_DIVIDE be set to a value of
33, which allows a settling time of 333 μs for each gain change.
By using the recommended setting for AGC_CLK_DIVIDE, the
total AGC settling time is
AGC Settling Time (sec)
Table 14. LNA/Mixer Modes (Register 9 Settings)
LNA_MODE
Receiver Mode (Bit DB25)
High Sensitivity 0
Mode (Default)
Enhanced Linearity, 0
High Gain
Medium Gain 1
Enhanced Linearity, 1
Medium Gain
Low Gain 1
Enhanced Linearity, 1
Low Gain
SEQ _ CLK _ DIVIDE (Hz)
AGC _ CLK _ DIVIDE
Number of AGC Gain Changes
=
AGC Update Rate (Hz)
LNA_GAIN
(Bits[DB21:DB20])
30
30
10
10
3
3
The total AFC settling time depends on the number of AGC
gain changes during reception of a packet. A total of five gain
changes gives a worst-case AGC settling time of 5 × 333 μs. To
allow for AGC settling, the preamble length should be adjusted
accordingly.
RSSI Formula (Converting to dBm)
The RSSI formula is
Input Power (dBm) = (−130 dBm + (Readback Code +
Gain Mode Correction)) × 0.5
where:
Readback Code is given by Bit RV7 to Bit RV1 in the readback
register (see Figure 57 and the Readback Format section).
Gain Mode Correction is given by the values in Table 13.
The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values
are also obtained from the readback register, as part of an RSSI
readback.
Table 13. Gain Mode Correction
LNA Gain
(LG2, LG1)
H (1, 0)
M (0, 1)
M (0, 1)
M (0, 1)
L (0, 0)
An additional factor should be introduced to account for losses
in the front-end-matching network/antenna.
Sensitivity (2FSK,
MIXER_LINEARITY
Data Rate = 4.8 kbps,
(Bit DB28) f = 4 kHz) (dBm)
DEV
0 −116.5
1 −113
0 −108
1 −102
0 −99
1 −91
Rev. 0 | Page 29 of 60
ADF7021-V
Filter Gain Gain Mode
(FG2, FG1) Correction
H (1, 0) 0
H (1, 0) 24
M (0, 1) 38
L (0, 0) 58
L (0, 0) 86
Rx Current
Consumption (mA)
20.1
20.1
17.9
17.9
17.9
17.9
Input IP3
(dBm)
−24
−20
−13.5
−9
−5
−3