Hardware Configuration; S1D13505 Configuration - Epson S1D13505F00A Technical Manual

6.3 Hardware Configuration
S1D13505 Configuration
The S1D13505 uses MD0 through MD15 to allow selection of the bus mode and other configuration
data on the rising edge of RESET#. Table 6-2 shows the settings used for the S1D13505 in this inter-
face.
Signal
MD0 8-bit host bus interface
MD1 See "Host Bus Selection" table below
MD2
MD3
MD4 Little Endian
MD5 Wait# signal is active high
MD6 See "Memory Configuration" table below
MD7
MD8 Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as GPIO4-11
MD9 Reserved
MD10 Active low (On) LCDPWR / GPO polarity
MD11 Alternate host bus interface
MD12 Reserved
MD13 Reserved
MD14 Reserved
MD15 Reserved
= required settings for MPC821 support.
MD11 MD3 MD2
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 x x
MD7 MD6
0 0
0 1
1 0
1 1
APPLICATION NOTES (X23A-G-005-05)
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6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
Table 6-2 S1D13505 Configuration Settings
1
16-bit host bus interface
See "Host Bus Selection" table below
Big Endian
Wait# signal is active low
See "Memory Configuration" table below
Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as DAC / CRT outputs
Configure SUSPEND# pin as Hardware Suspend Enable
Active high (On) LCDPWR / GPO polarity
Primary host bus interface
Reserved
Reserved
Reserved
Reserved
Table 6-3 Host Bus Selection
MD1 Option Host Bus Interface
0 1 SH-3/SH-4 bus interface
1 2 MC68K Bus 1
0 3 MC68K Bus 2
1 4 Generic
0 5 Reserved
1 6 MIPS/ISA
0 7 Power PC
1 8 PC Card (PCMCIA)
x 9+ Reserved
Table 6-4 Memory Configuration
Option Memory Selection
1 Symmetrical 256K x 16 DRAM
2 Symmetrical 1M x 16 DRAM
3 Asymmetrical 256K x 16 DRAM
4 Asymmetrical 1M x 16 DRAM
EPSON
0
5-27