Epson S1D13505F00A Technical Manual page 28

5: PINS
Pin Name Type Pin # Driver
WE0# I 8
WAIT# O 15 TS2
RESET# I 11
1-16
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Table 5-1 Host Interface Pin Descriptions
Reset#
State
This is a multi-purpose pin:
• For SH-3/SH-4 Bus, this pin inputs the write enable signal for the lower
data byte (WE0#).
• For MC68K Bus 1, this pin must be connected to V
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic Bus, this pin inputs the write enable signal for the lower
data byte (WE0#).
• For MIPS/ISA Bus, this pin inputs the memory write signal (MEMW#).
CS Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the memory write com-
mand (/WE).
• For Toshiba TX3912 Bus, this pin inputs the memory write command
(WE*).
• For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1).
• For PC Card (PCMCIA) Bus, this pin inputs the write enable signal (-WE).
See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respec-
tive AC Timing diagram for detailed functionality.
The active polarity of the WAIT# output is configurable; the state of MD5
on the rising edge of RESET# defines the active polarity of WAIT# - see
"Summary of Configuration Options".
• For SH-3 Bus, this pin outputs the wait request signal (WAIT#); MD5
must be pulled low during reset by the internal pull-down resistor.
• For SH-4 Bus, this pin outputs the ready signal (RDY#); MD5 must be
pulled high during reset by an external pull-up resistor.
• For MC68K Bus 1, this pin outputs the data transfer acknowledge signal
(DTACK#); MD5 must be pulled high during reset by an external pull-
up resistor.
• For MC68K Bus 2, this pin outputs the data transfer and size acknowl-
edge bit 1 (DSACK1#); MD5 must be pulled high during reset by an
external pull-up resistor.
• For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must
be pulled high during reset by an external pull-up resistor.
Hi-Z • For MIPS/ISA Bus, this pin outputs the IO channel ready signal
(IOCHRDY); MD5 must be pulled low during reset by the internal pull-
down resistor.
• For Philips PR31500/31700 Bus, this pin outputs the wait state signal
(/CARDxWAIT); MD5 must be pulled low during reset by the inter-
nal pull-down resistor.
• For Toshiba TX3912 Bus, this pin outputs the wait state signal (CARDx-
WAIT*); MD5 must be pulled low during reset by the internal pull-down
resistor.
• For PowerPC Bus, this pin outputs the transfer acknowledge signal
(TA#); MD5 must be pulled high during reset by an external pull-up
resistor.
• For PC Card (PCMCIA) Bus, this pin outputs the wait signal (-WAIT);
MD5 must be pulled low during reset by the internal pull-down resistor.
See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respec-
tive AC Timing diagram for detailed functionality.
Active low input that clears all internal registers and forces all outputs to
CS – their inactive states. Note that active high RESET signals must be inverted
before input to this pin.
EPSON
Description
DD
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)