Registers - Epson S1D13505F00A Technical Manual

5: ADVANCED TECHNIQUES

Registers

REG[10h] Screen 1 Display Start Address 0
Start Address Start Address Start Address
Bit 7 Bit 6 Bit 5
REG[11h] Screen 1 Display Start Address 1
Start Address Start Address Start Address
Bit 15 Bit 14 Bit 13
REG[12h] Screen 1 Display Start Address 2
n/a n/a
These three registers form the address of the word in the display buffer where screen 1 will start dis-
playing from. Changing these registers by one will cause a change of 0 to 16 pixels depending on the
current color depth. Refer to the following table to see the minimum number of pixels affected by a
change of one to these registers.
Table 5-1 Number of Pixels Panned Using Start Address
Color Depth (bpp)
1
2
4
8
15
16
REG[18h] Pixel Panning Register
Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel
Pan Pan
Bit 3 Bit 2 Bit 1
The pixel panning register offers finer control over pixel pans than is available with the Start
Address Registers. Using this register it is possible to pan the displayed image one pixel at a time.
Depending on the current color depth certain bits of the pixel pan register are not used. The follow-
ing table shows this.
2-18
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Start Address Start Address Start Address
Bit 4 Bit 3 Bit 2
Start Address Start Address Start Address
Bit 12 Bit 11 Bit 10
Start Address Start Address
n/a n/a
Bit 19 Bit 18
Figure 5-3 Screen 1 Start Address Registers
Pixels Per Word Number of Pixels Panned
16
8
4
2
1
1
Screen 2 Pixel Screen 1 Pixel Screen 1 Pixel
Pan Pan Pan
Bit 0 Bit 3 Bit 2
Figure 5-4 Pixel Panning Register
Table 5-2 Active Pixel Pan Bits
Color Depth (bpp) Pixel Pan Bits Used
1 bits [3:0]
2 bits [2:0]
4 bits [1:0]
8 bit 0
15/16 ---
EPSON
Start Address Start Address
Bit 1 Bit 0
Start Address Start Address
Bit 9 Bit 8
Start Address Start Address
Bit 17 Bit 16
16
8
4
2
1
1
Screen 1 Pixel Screen 1 Pixel
Pan Pan Pan
Bit 1 Bit 0
S1D13505 PROGRAMMING NOTES
AND EXAMPLES (X23A-G-003-05)