Table 7-3 Mc68000 Timing - Epson S1D13505F00A Technical Manual

Symbol
t1 Clock period
t2 Clock pulse width high
t3 Clock pulse width low
t4 A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either
UDS# = 0 or LDS# = 0
t5 A[20:1], M/R# hold from AS#
t6 CS# hold from AS#
t7 R/W# setup to before to either UDS# = 0 or LDS# = 0
t8 R/W# hold from AS#
t9 #1 AS# = 0 and CS# = 0 to DTACK# driven high
t10 AS# high to DTACK# high
t11 First BCLK where AS# = 1 to DTACK# high impedance
t12 D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either UDS# =
0 or LDS# = 0 (write cycle)
t13 D[15:0] hold from falling edge of DTACK# (write cycle)
#2 Falling edge of UDS# = 0 or LDS# = 0 to DB driven (read cycle)
t14
t15 D[15:0] valid to DTACK# falling edge (read cycle)
t16 UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle)
t17 AS# high setup to CLK
#1. If the S1D13505 host interface is disabled, the timing for DTACK# driven high is relative to the falling
edge of CS#, AS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is
later.
#2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of
UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later.
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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Table 7-3 MC68000 Timing

Parameter
Min.
20
6
6
10
0
0
10
0
0
3
10
0
0
0
5
2
EPSON
7: A.C. CHARACTERISTICS
3.3V 5.0V
Units
Max. Min. Max.
20 ns
6 ns
6 ns
10 ns
0 ns
0 ns
10 ns
0 ns
0 ns
18 3 12 ns
25 10 ns
10 ns
0 ns
0 ns
0 ns
25 2.5 10 ns
2 ns
1-31