Powerpc Interface Timing (E.g. Mpc8Xx, Mc68040, Coldfire); Figure 7-12 Powerpc Timing; Table 7-12 Powerpc Timing - Epson S1D13505F00A Technical Manual

PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
t1
CLKOUT
A[11:31], RD/WR#
TSIZ[0:1], M/R#
CS#
TS#
TA#
BI#
D[0:15](write)
D[0:15](read)
Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option
is selected.
Symbol
t1 Clock period
t2 Clock pulse width high
t3 Clock pulse width low
t4 AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup
t5 AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold
t6 CS# setup
t7 CS# hold
t8 TS# setup
t9 TS# hold
t10 CLKOUT to TA# driven
t11 CLKOUT to TA# low
t12 CLKOUT to TA# high
t13 negative edge CLKOUT to TA# tri-state
t14 CLKOUT to BI# driven
t15 CLKOUT to BI# high
t16 negative edge CLKOUT to BI# tri-state
t17 DB[15:0] setup to 2nd CLKOUT after TS# = 0 (write cycle)
t18 DB[15:0] hold (write cycle)
t19 CLKOUT to DB driven (read cycle)
t20 DB[15:0] valid to TA# falling edge (read cycle)
t21 CLKOUT to DB[15:0] tri-state (read cycle)
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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t2 t3
t4
t6
t8 t9
t10
t14
t17
t19

Figure 7-12 PowerPC Timing

Table 7-12 PowerPC Timing

Parameter
Min.
25
6
6
10
0
10
0
7
5
0
3
3
5
0
3
5
10
0
0
0
5
EPSON
7: A.C. CHARACTERISTICS
t5
t7
t11 t12 t13
t15 t16
t18
t20 t21
3.0V 5.0V
Units
Max. Min. Max.
20 ns
6 ns
6 ns
10 ns
0 ns
10 ns
0 ns
10 ns
0 ns
0 ns
19 3 12 ns
19.7 3 13 ns
25 2.5 10 ns
18 0 11 ns
16 3 10 ns
25 2.5 10 ns
10 ns
0 ns
0 ns
0 ns
25 2.5 10 ns
1-45