Figure 7-2 Sh-3 Timing - Epson S1D13505F00A Technical Manual

Embedded ramdac lcd/crt controller
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7: A.C. CHARACTERISTICS
SH-3 Interface Timing
t1
t2
CKIO
t4
A[20:0], M/R#
RD/WR#
t6
BS#
t8
CSn#
WEn#
RD#
WAIT#
D[15:0](write)
D[15:0](read)
Notes: • The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is se-
lected.
• The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to
a non-zero value.
1-28
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t3
t7
t12
t9
t12
t11
t13

Figure 7-2 SH-3 Timing

EPSON
S1D13505F00A HARDWARE FUNCTIONAL
t5
t10
t14
t15
t16
SPECIFICATION (X23A-A-001-12)

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