Epson S1D13505F00A Technical Manual page 101

Pixel Panning Register
REG[18h]
Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel
Panning Bit 3 Panning Bit 2 Panning Bit 1
This register is used to control the horizontal pixel panning of Screen 1 and Screen 2.
Each screen can be independently panned to the left by programming its respective Pixel
Panning Bits to a non-zero value. The value represents the number of pixels panned. The
maximum pan value is dependent on the display mode.
Display Mode
Smooth horizontal panning can be achieved by a combination of this register and the Dis-
play Start Address registers.
See Section 10, "Display Configuration" for details.
bits 7–4 Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
bits 3–0 Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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Screen 2 Pixel Screen 1 Pixel Screen 1 Pixel
Panning Bit 0 Panning Bit 3 Panning Bit 2
Table 8-8 Pixel Panning Selection
Maximum Pan Value
1 bpp 16
2 bpp 8
4 bpp 4
8 bpp 1
15/16 bpp 0
EPSON
8: REGISTERS
RW
Screen 1 Pixel Screen 1 Pixel
Panning Bit 1 Panning Bit 0
Pixel Panning Bits Active
Bits [3:0]
Bits [2:0]
Bits [1:0]
Bit 0
none
1-89