Power Save Configuration Registers - Epson S1D13505F00A Technical Manual

Power Save Configuration Registers
Power Save Configuration Register
REG[1Ah]
Power Save
Status n/a
RO
bit 7 Power Save Status
This is a read-only status bit.
This bit indicates the power-save state of the chip.
When this bit = 1, the panel has been powered down and the memory controller is either
in self refresh mode or is performing only
When this bit = 0, the chip is either powered up, in transition of powering up, or in transi-
tion of powering down. See Section 15, "Power Save Modes" for details.
bit 3 LCD Power Disable
This bit is used to override the panel on/off sequencing logic.
When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic.
When this bit = 1 the LCDPWR output is directly forced to the off state.
The LCDPWR "On/Off" polarity is configured by MD10 at the rising edge of RESET#
(MD10 = 0 configures LCDPWR = 0 as the Off state; MD10 = 1 configures LCDPWR =
1 as the Off state).
bits 2–1 Suspend Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh to use in Suspend mode.
Suspend Refresh Select Bits [1:0]
Note: These bits should not be changed when suspend mode is active.
bit 0 Software Suspend Mode Enable
When this bit = 1 software Suspend mode is enabled.
When this bit = 0 software Suspend mode is disabled.
See Section 15, "Power Save Modes" for details.
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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Suspend
LCD Power
n/a n/a Refresh Select
Disable
Bit 1
CAS-before-RAS
Table 8-10 Suspend Refresh Selection
00 CAS-before-RAS (CBR) refresh
01
1x
EPSON
8: REGISTERS
RW
Suspend Software
Refresh Select Suspend Mode
Bit 0 Enable
refresh cycles.
DRAM Refresh Type
Self-Refresh
No Refresh
1-91