Epson S1D13505F00A Technical Manual page 11

CONTENTS
Table 5-1 Host Interface Pin Descriptions.......................................................................................... 1-13
Table 5-2 Memory Interface Pin Descriptions .................................................................................... 1-17
Table 5-3 LCD Interface Pin Descriptions .......................................................................................... 1-18
Table 5-4 Clock Input Pin Description ................................................................................................ 1-18
Table 5-5 Miscellaneous Interface Pin Descriptions .......................................................................... 1-19
Table 5-6 Summary of Power On / Reset Options ............................................................................. 1-20
Table 5-7 CPU Interface Pin Mapping ............................................................................................... 1-20
Table 5-8 Memory Interface Pin Mapping .......................................................................................... 1-21
Table 5-9 LCD Interface Pin Mapping ................................................................................................ 1-22
Table 6-1 Absolute Maximum Ratings ............................................................................................... 1-24
Table 6-2 Recommended Operating Conditions ................................................................................ 1-24
Table 6-3 Electrical Characteristics for V
Table 6-4 Electrical Characteristics for V
Table 6-5 Electrical Characteristics for V
Table 7-1 SH-4 Timing ....................................................................................................................... 1-27
Table 7-2 SH-3 Timing ....................................................................................................................... 1-29
Table 7-3 MC68000 Timing................................................................................................................ 1-31
Table 7-4 MC68030 Timing................................................................................................................ 1-33
Table 7-5 PC Card Interface Timing .................................................................................................. 1-35
Table 7-6 Generic Timing................................................................................................................... 1-37
Table 7-7 MIPS/ISA Timing................................................................................................................ 1-39
Table 7-8 Philips Timing..................................................................................................................... 1-41
Table 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus ...................................... 1-41
Table 7-10 Toshiba Timing .................................................................................................................. 1-43
Table 7-11 Clock Input Requirements for BUSCLK Using Toshiba Local Bus .................................... 1-44
Table 7-12 PowerPC Timing ................................................................................................................ 1-45
Table 7-13 Clock Input Requirements for CLKI Divided Down Internally (MCLK = CLKI/2) ................ 1-46
Table 7-14 Clock Input Requirements for CLKI ................................................................................... 1-46
Table 7-15 EDO DRAM Read Timing .................................................................................................. 1-48
Table 7-16 EDO DRAM CAS Before RAS Refresh Write Timing......................................................... 1-49
Table 7-17 EDO-DRAM Self-Refresh Timing....................................................................................... 1-50
Table 7-18 FPM-DRAM Read/Write/Read-Write Timing...................................................................... 1-52
Table 7-19 FPM-DRAM CAS before RAS Refresh Timing .................................................................. 1-53
Table 7-20 FPM DRAM Self-Refresh Timing ....................................................................................... 1-54
Table 7-21 LCD Panel Power Off/ Power On....................................................................................... 1-55
Table 7-22 Power Save Status and Local Bus Memory Access Relative to Power Save Mode.......... 1-56
Table 7-23 4-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-58
Table 7-24 8-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-60
Table 7-25 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................ 1-62
Table 7-26 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1).......................................... 1-64
Table 7-27 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2).......................................... 1-66
Table 7-28 16-Bit Single Color Passive LCD Panel A.C. Timing ......................................................... 1-68
Table 7-29 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing.................................................. 1-70
Table 7-30 8-Bit Dual Color Passive LCD Panel A.C. Timing .............................................................. 1-72
Table 7-31 16-Bit Dual Color Passive LCD Panel A.C. Timing ............................................................ 1-74
Table 7-32 16-Bit TFT/D-TFD A.C. Timing........................................................................................... 1-76
Table 7-33 CRT A.C. Timing ................................................................................................................ 1-78
Table 8-1 S1D13505 Addressing ....................................................................................................... 1-79
Table 8-2 DRAM Refresh Rate Selection .......................................................................................... 1-80
Table 8-3 Panel Data Width Selection ............................................................................................... 1-81
Table 8-4 FPLINE Polarity Selection.................................................................................................. 1-83
Table 8-5 FPFRAME Polarity Selection ............................................................................................. 1-85
Table 8-6 Simultaneous Display Option Selection ............................................................................. 1-86
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List of Tables
= 5.0V Typical ............................................................... 1-24
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= 3.3V Typical ............................................................... 1-24
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= 3.0V Typical ............................................................... 1-25
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EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)