Miscellaneous; Table 5-5 Miscellaneous Interface Pin Descriptions - Epson S1D13505F00A Technical Manual

Miscellaneous

Pin Name Type Pin #
SUSPEND# IO 71 CS/TS1
CLKI I 69
TESTEN I 70
12, 33, 55,
V P
DD
72, 97, 109
99, 102,
DACV P
DD
104
14, 32, 50,
V P 68, 78, 87,
SS
96, 110
DACV P 98, 106
SS
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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Table 5-5 Miscellaneous Interface Pin Descriptions

Cell RESET# State
This pin can be used as a power-down input (SUSPEND#) or as an
output possibly used for controlling the LCD backlight power:
• When MD9 = 0 at rising edge of RESET#, this pin is an active-
Hi-Z if MD[9]=0 low Schmitt input used to put the S1D13505 into Hardware sus-
High pend mode - see "15 Power Save Modes" for details.
if MD[10:9]=01 • When MD[10:9] = 01 at rising edge of RESET#, this pin is an
Low output (GPO) with a reset state of 1. Its state is controlled by
if MD[10:9]=11 REG[21h] bit 7.
• When MD[10:9] = 11 at rising edge of RESET#, this pin is an
output (GPO) with a reset state of 0. Its state is controlled by
REG[21h] bit 7.
Input clock for the internal pixel clock (PCLK) and memory clock
C (MCLK). PCLK and MCLK are derived from CLKI - see REG[19h]
for details.
Test Enable. This pin should be connected to V
CD Hi-Z
tion.
V
DD
P
DAC V
DD
P
V
SS
P
P DAC V
SS
EPSON
5: PINS
Description
for normal opera-
SS
1-19