Epson S1D13505F00A Technical Manual page 9

CONTENTS
Figure 3-1 Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM) ...................................... 1-4
Figure 3-2 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM) ...................................... 1-4
Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM)......... 1-5
Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM)......... 1-5
Figure 3-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM) ..................................... 1-6
Figure 3-6 Typical System Diagram (NEC V
Figure 3-7 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM) ....... 1-7
Figure 3-8 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM) ....................... 1-7
Figure 3-9 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM) .............................. 1-8
Figure 3-10 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM) .................. 1-8
Figure 4-1 System Block Diagram Showing Datapaths ........................................................................ 1-9
Figure 5-1 Pinout Diagram .................................................................................................................. 1-11
Figure 5-2 External Circuitry for CRT Interface ................................................................................... 1-23
Figure 7-1 SH-4 Timing ....................................................................................................................... 1-26
Figure 7-2 SH-3 Timing ....................................................................................................................... 1-28
Figure 7-3 MC68000 Timing................................................................................................................ 1-30
Figure 7-4 MC68030 Timing................................................................................................................ 1-32
Figure 7-5 PC Card Interface Timing .................................................................................................. 1-34
Figure 7-6 Generic Timing................................................................................................................... 1-36
Figure 7-7 MIPS/ISA Timing................................................................................................................ 1-38
Figure 7-8 Philips Timing..................................................................................................................... 1-40
Figure 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus ...................................... 1-41
Figure 7-10 Toshiba Timing .................................................................................................................. 1-42
Figure 7-11 Clock Input Requirements.................................................................................................. 1-44
Figure 7-12 PowerPC Timing ................................................................................................................ 1-45
Figure 7-13 Clock Input Requirements.................................................................................................. 1-46
Figure 7-14 EDO-DRAM Read/Write Timing......................................................................................... 1-47
Figure 7-15 EDO-DRAM Read-Write Timing......................................................................................... 1-47
Figure 7-16 EDO-DRAM CAS Before RAS Refresh Write Timing ........................................................ 1-49
Figure 7-17 EDO-DRAM Self-Refresh Timing....................................................................................... 1-50
Figure 7-18 FPM-DRAM Read/Write Timing ......................................................................................... 1-51
Figure 7-19 FPM-DRAM Read-Write Timing......................................................................................... 1-51
Figure 7-20 FPM-DRAM CAS before RAS Refresh Timing .................................................................. 1-53
Figure 7-21 FPM-DRAM Self-Refresh Timing ....................................................................................... 1-54
Figure 7-22 LCD Panel Power Off / Power On Timing. Drawn with LCDPWR Set to Active High Polarity1-
55
Figure 7-23 Power Save Status and Local Bus Memory Access Relative to Power Save Mode.......... 1-56
Figure 7-24 4-Bit Single Monochrome Passive LCD Panel Timing ....................................................... 1-57
Figure 7-25 4-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-58
Figure 7-26 8-Bit Single Monochrome Passive LCD Panel Timing ....................................................... 1-59
Figure 7-27 8-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-60
Figure 7-28 4-Bit Single Color Passive LCD Panel Timing ................................................................... 1-61
Figure 7-29 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................ 1-62
Figure 7-30 8-Bit Single Color Passive LCD Panel Timing (Format 1).................................................. 1-63
Figure 7-31 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1).......................................... 1-64
Figure 7-32 8-Bit Single Color Passive LCD Panel Timing (Format 2).................................................. 1-65
Figure 7-33 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2).......................................... 1-66
Figure 7-34 16-Bit Single Color Passive LCD Panel Timing ................................................................. 1-67
Figure 7-35 16-Bit Single Color Passive LCD Panel A.C. Timing ......................................................... 1-68
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List of Figures
41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM)................. 1-6
R
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)