Memory Interface; Table 5-2 Memory Interface Pin Descriptions - Epson S1D13505F00A Technical Manual

Memory Interface

Pin Name Type Pin #
LCAS# O 51
UCAS# O 52
WE# O 53
RAS# O 54
34, 36, 38,
40, 42, 44,
46, 48, 49,
MD[15:0] IO
47, 45, 43,
41, 39, 37,
35
58, 60, 62,
MA[8:0] O 64, 66, 67,
65, 63, 61
MA9 IO 56
MA10 IO 59
MA11 IO 57
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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Table 5-2 Memory Interface Pin Descriptions

Reset#
Driver
State
• For dual-CAS# DRAM, this is the column address strobe for the lower
byte (LCAS#).
CO1 1 • For single-CAS# DRAM, this is the column address strobe (CAS#).
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For dual-CAS# DRAM, this is the column address strobe for the upper
byte (UCAS#).
CO1 1 • For single-CAS# DRAM, this is the write enable signal for the upper
byte (UWE#).
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
• For dual-CAS# DRAM, this is the write enable signal (WE#).
• For single-CAS# DRAM, this is the write enable signal for the lower
CO1 1 byte (LWE#).
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
Row address strobe - see Memory Interface Timing for detailed function-
CO1 1
ality.
• Bi-Directional memory data bus.
• During reset, these pins are inputs and their states at the rising edge of
RESET# are used to configure the chip - see Summary of Configuration
C/TS1D Hi-Z Options. Internal pull-down resistors (typical values of 100KΩ/180ΚΩ
at 5V/3.3V respectively) pull the reset states to 0. External pull-up resis-
tors can be used to pull the reset states to 1.
See Memory Interface Timing for detailed functionality.
Multiplexed memory address - see Memory Interface Timing for function-
CO1 Output ality.
This is a multi-purpose pin:
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address bit 9
(MA9).
• For symmetrical 512K byte DRAM, this pin can be used as general pur-
C/TS1 Output
pose IO pin 3 (GPIO3).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 10
(MA10).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can
C/TS1 Output be used as general purpose IO pin 1 (GPIO1).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 11
(MA11).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can
C/TS1 Output be used as general purpose IO pin 2 (GPIO2).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See "Table 5-8 Memory Interface Pin Mapping" for summary. See Mem-
ory Interface Timing for detailed functionality.
EPSON
5: PINS
Description
1-17