Comments - Epson S1D13505F00A Technical Manual

Embedded ramdac lcd/crt controller

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• It is assumed that the 13505CFG user is familiar with S1D13505 hardware and software. Refer to

the "S1D13505 Functional Hardware Speciﬁcation" and the "S1D13505 Programming Notes

and Examples" for more details.

• 13505CFG veriﬁes that the given conﬁguration meets the limitations in the hardware speciﬁca-

tion. Part of this veriﬁcation process is as follows:

1. The divide ratio for the source clock/MClk is determined based on Table 14-3: Example Frame

Rates with Ink Disabled from the Functional Hardware Speciﬁcation. According to this table,

MClk cannot exceed 40 MHz for 50ns EDO-DRAM, MClk cannot exceed 33 MHz for 60ns

EDO-DRAM, and MClk cannot exceed 25 MHz for 60ns FPM-DRAM. If MClk exceeds the

maximum value, the MCLK value is set to the source clock divided by two ( MClk = source clock

/ 2). Otherwise the MCLK value is set to the source clock ( MClk = source clock) . 13505CFG

shows the MClk value on the General Page.

2. The divide ratio for MClk/PClk is determined based on Table 14-1: Maximum PCLK Frequency

with EDO-DRAM and Table 14-2: Maximum PCLK Frequency with FPM-DRAM . Once this

ratio is determined, PClk = MClk / ratio . Note that there are two PClk divide ratios based on the

three display modes: panel, CRT, and simultaneous display (CRT and simultaneous display use

the same ratio). 13505CFG shows the PClk values for these three modes on the General Page.

3. The HNDP and VNDP values are calculated based on the desired frame rate for each of the three

modes (panel, CRT, simultaneous), the display's HDP (X resolution), VDP (Y resolution), and

maximum PCLK as calculated in step 3.

4. If it is not possible to reach the desired frame rate within 5%, an error message is shown when

saving the conﬁguration.

• When conﬁguring either the CRT or TFT/D-TFD panel, the PClk must be the same as the required

VESA frequency for the given VESA mode. The following VESA modes are supported:

Resolution

640x480

800x600

• 13505CFG does not support 50ns FPM-DRAM.

• 13505CFG programs TFT/D-TFD panels with the same VESA timings as a CRT, so the CRT

restrictions shown in the hardware speciﬁcation also apply to TFT/D-TFD panels. Consequently

for TFT/D-TFD panels, use the CRT frame rate and CRT PCLK as described above.

• For simultaneous display, select a CRT VESA mode, and use the CRT's frame rate for the panel's

frame rate.

UTILITIES (X23A-B-001-02)

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1: 13505CFG CONFIGURATION PROGRAM

PCLK

FrameRate

--------------------------------------------------------------------------------------- -

(

)

(

HDP

HNDP

VDP

Frame Rate

PCLK (MHz)

Supported DRAM Types

(Hz)

50ns EDO, 60ns EDO,

25.175

70ns EDO, 60ns FPM

31.500

50ns EDO, 60ns EDO

31.500

50ns EDO, 60ns EDO

36.000

40.000

EPSON

)

VNDP

50ns EDO

3-11

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