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2.9.3
MIPI 34 interface signals
The table describes the signals on the MIPI 34 interface.
Signal
I/O
TDI
Output
TDO
Input
TMS
Output
TCK
Output
RTCK
Input
nTRST
Output
TRST_PD
Output
nSRST
Input/
Output
DBGRQ
Output
DBGACK
Input
SWDIO (SWD
Input/
mode)
Output
SWCLK(SWD
Output
mode)
SWO (SWD mode)
Input
TraceD[0-3]
Input
ARM 100956_0527_00_en
Description
The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH
on the target.
The Test Data Out pin receives serial data from the target during debugging. You are advised to
series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS
can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled
HIGH on the target.
The Return Test Clock pin echos the test clock signal back to DSTREAM for use with adaptive
mode clocking. If RTCK is generated by the target processor, you are advised to series terminate
it. RTCK can be pulled HIGH or LOW on the target when not in use.
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a
reset. The polarity and strength of nTRST is configurable.
The Test Reset (Pull-Down) pin resets the TAP controller of the processor to allow debugging to
take place. TRST_PD is typically pulled LOW on the target (reset state) and pulled strong-HIGH
by DSTREAM to enable debugging. The polarity and strength of TRST_PD is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the
target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the
target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is
configurable.
The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely
used by current systems and is usually pulled LOW on the target.
The Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the
target processor is now in debug state. DBGACK is rarely used by current systems and is usually
pulled LOW on the target.
The Serial Wire Data I/O pin sends and receives serial data to and from the target during
debugging. You are advised to series terminate SWDIO close to the target processor.
The Serial Wire Clock pin clocks data into and out of the target during debugging.
The Serial Wire Output pin provides trace data to DSTREAM. You are advised to series terminate
SWO close to the target processor.
The Trace Data [0-3] pins provide DSTREAM with Trace Port Interface Unit (TPIU) continuous
mode trace data from the target. You are advised to series terminate these signals close to the target
processor.
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2 ARM DSTREAM Target Interface Connections
2.9 The MIPI 34 connector pinouts and interface signals
Table 2-16 MIPI 34 interface pinout table (continued)
Pin Signal name I/O diagram Voltage domain
33
GND
H
34
VTREF
F
NA
B
Table 2-17 MIPI 34 signals
2-47
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