ARM DS-5 Manual page 32

Signal I/O
nTRST Output
nSRST Input/
Output
DBGRQ Output
DBGACK Input
VTREF Input
VSUPPLY -
GND -
ARM 100956_0527_00_en
Description
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a
reset. The polarity and strength of nTRST is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the
target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the
target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is
configurable.
The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely
used by current systems and is usually pulled LOW on the target.
The Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the
target processor is now in debug state. DBGACK is rarely used by current systems and is usually
pulled LOW on the target.
The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to
match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a
resistor, its value must be no greater than 100Ω.
The Voltage Supply pin is not used by DSTREAM and must be left unconnected.
Ground.
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2 ARM DSTREAM Target Interface Connections
2.3 The Mictor 38 connector pinouts and interface signals
Table 2-5 Mictor 38 signals (continued)
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