Coresight 20 Interface Pinout Table; Table 2-15 Coresight 20 Signals - ARM DS-5 Manual

2.8.3 CoreSight 20 interface signals
The table describes the signals on the CoreSight 20 interface.
Signal I/O
TDI Output
TDO Input
TMS Output
TCK Output
RTCK Input
ARM 100956_0527_00_en
Description
The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH
on the target.
The Test Data Out pin receives serial data from the target during debugging. You are advised to
series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target.
TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically
pulled HIGH on the target.
The Return Test Clock pin echos the test clock signal back to DSTREAM for use with adaptive
mode clocking. If RTCK is generated by the target processor, you are advised to series terminate
it. RTCK can be pulled HIGH or LOW on the target when not in use.
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2 ARM DSTREAM Target Interface Connections
2.8 The CoreSight 20 connector pinouts and interface signals
Table 2-14 CoreSight 20 interface pinout table
Pin Signal name
1 VTREF
2 TMS/SWDIO
3 GND
4 TCK/SWCLK
5 GND
6 TDO/SWO
7 KEY (NC)
8 TDI
9 GND
10 nSRST
11 NC
12 RTCK/TRACECLK A
13 NC
14 SWO/TraceD0
15 GND
16 nTRST/TraceD1
17 GND
18 DBGRQ/TraceD2
19 GND
20 DBGACK /TraceD3 A

Table 2-15 CoreSight 20 signals

I/O diagram Voltage domain
G A
B/C A
H NA
B A
H NA
A A
NA NA
B A
H NA
E A
I NA
A
I NA
E A
H NA
E A
H NA
A A
H NA
A
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