Figure 2-1 Jtag Port Timing Diagram; Table 2-1 Dstream Jtag Characteristics - ARM DS-5 Manual

TCK
TDI
TMS
TDO
Issues with minimum setup and hold times can always be resolved by decreasing the TCK frequency,
because this increases the separation between signals changing and being sampled.
There are no separate timing requirements for the adaptive clocking mode. In adaptive mode, the
DSTREAM unit samples TDO on the rising edge of RTCK and not TCK, so TDO timing is relative to
RTCK.
The following table shows the timing requirements for the JTAG signals on the DSTREAM probe:
Related concepts
2.1.3 About trace signals on page 2-26.
Related references
2.1 Signal descriptions on page 2-23.
2.1.2 Serial Wire Debug on page 2-25.
ARM 100956_0527_00_en
Note
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
2 ARM DSTREAM Target Interface Connections
Target device
samples TDI and
TMS
T
clk

Table 2-1 DSTREAM JTAG Characteristics

Parameter Min
T
clk
T
ds
Non-Confidential
2.1 Signal descriptions
Target device sets-up
TDO

Figure 2-1 JTAG port timing diagram

Max Description
16.67ns 100ms TCK period
49% 51% TCK Duty Cycle
2-24